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| rev. 1.6 october 2002 1/178 st72321r/ar 8-bit mcu with nested interrupts, flash, 10-bit adc, five timers, spi, sci, i 2 c interface n memories C 32k to 60k dual voltage high density flash (hdflash) or rom with read-out protection capability. in-application programming and in-circuit programming for hdflash devices C 1k to 2k ram C hdflash endurance: 100 cycles, data reten- tion: 20 years at 55c n clock, reset and supply management C enhanced low voltage supervisor (lvd) for main supply and auxiliary voltage detector (avd) with interrupt capability C clock sources: crystal/ceramic resonator os- cillators, internal or external rc oscillator, clock security system and bypass for external clock C pll for 2x frequency multiplication C four power saving modes: halt, active-halt, wait and slow n interrupt management C nested interrupt controller C 14 interrupt vectors plus trap and reset C top level interrupt (tli) pin C 15 external interrupt lines (on 4 vectors) n up to 48 i/o ports C 48 multifunctional bidirectional i/o lines C 34 alternate function lines C 16 high sink outputs n 5 timers C main clock controller with: real time base, beep and clock-out capabilities C configurable watchdog timer C two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, pwm and pulse generator modes C 8-bit pwm auto-reload timer with: 2 input cap- tures, 4 pwm outputs, output compare and time base interrupt, external clock with event detector n 3 communications interfaces C spi synchronous serial interface C sci asynchronous serial interface (lin com- patible) Ci 2 c multimaster interface n 1 analog peripheral C 10-bit adc with 16 input pins n instruction set C 8-bit data manipulation C 63 basic instructions C 17 main addressing modes C 8 x 8 unsigned multiply instruction n development tools C full hardware/software development package C in-circuit testing capability device summary tqfp64 10 x 10 tqfp64 14 x 14 features st72(f)321(r/ar)9 st72(f)321(r/ar)7 st72(f)321(r/ar)6 program memory - bytes 60k 48k 32k ram (stack) - bytes 2048 (256) 1536 (256) 1024 (256) operating voltage 3.8v to 5.5v temp. range (rom) up to - 40c to +125c temp. range (flash) up to -40c to +125c -40c to +85 c package tqfp64 14x14 (r), tqfp64 10x10 (ar) 1
table of contents 178 2/178 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.1 read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3.4 internal low voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.2 auxiliary voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.3 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.6.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.7 external interrupt control register (eicr) . . . . . . . . . . . . . . . . . . . . . . . 38 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2 table of contents 3/178 8.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4.1 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 9.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5.1 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 10.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.4 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.6 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.7 using halt mode with the wdg (wdghalt option) . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2 main clock controller with real time clock and beeper (mcc/rtc) . 56 10.2.1 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.3 real time clock timer (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.4 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.3 pwm auto-reload timer (art) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 10.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.4.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 1 table of contents 178 4/178 10.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.5.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.5.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.5.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.5.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.6 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 10.6.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.6.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.6.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.6.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.7 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.7.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.7.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.7.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.7.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.8 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.8.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.8.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 30 11.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 12.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 12.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 1 table of contents 5/178 12.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . 138 12.3.3 auxiliary voltage detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.3.4 external voltage detector (evd) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.4.1 run and slow modes (flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.4.2 wait and slow wait modes (flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.4.3 run and slow modes (rom devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.4.4 wait and slow wait modes (rom devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.4.5 halt and active-halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.4.6 supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.4.7 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5.1 general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5.3 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.4 rc oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 12.5.5 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.5.6 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.6.1 ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.6.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.7.1 functional ems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.7.2 electro magnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.7.3 absolute electrical sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.7.4 esd pin protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.8.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.9.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.9.2 iccsel/vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.10.18-bit pwm-art auto-reload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.10.216-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 161 12.11.1spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.11.2i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.12 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.12.1adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 1 table of contents 6/178 13.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14 st72321r/ar device configuration and ordering information . . . . . . . . . . 170 14.1 flash option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.2 device ordering information and transfer of customer code . . . . 172 14.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.1 socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 1 st72321r/ar 7/178 1 introduction the st72321r and st72321ar devices are members of the st7 microcontroller family de- signed for mid-range applications all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set and are available with flash or rom pro- gram memory. under software control, all devices can be placed in wait, slow, active-halt or halt mode, reducing power consumption when the application is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. figure 1. device block diagram 8-bit core alu address and data bus osc1 v pp control program (16k - 60k bytes) v dd reset port f pf7:0 (8-bits) timer a beep port a ram (512 - 2048 bytes) port c 10-bit adc v aref v ssa port b pb7:0 (8-bits) pwm art port e pe7:0 (8-bits) sci timer b pa7:0 (8-bits) port d pd7:0 (8-bits) spi pc7:0 (8-bits) v ss watchdog tli osc lvd osc2 memory mcc/rtc/beep evd avd i2c 3 st72321r/ar 8/178 2 pin description figure 2. 64-pin tqfp 14x14 and 10x10 package pinout v aref v ssa v dd_3 v ss_3 mco / ain8 / pf0 beep / (hs) pf1 (hs) pf2 ocmp2_a / ain9 / pf3 ocmp1_a / ain10 / pf4 icap2_a / ain11 / pf5 icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain4 / pd4 ain5 / pd5 ain6 / pd6 ain7 / pd7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei3 ei0 ei1 pwm3 / pb0 pwm2 / pb1 pwm1 / pb2 pwm0 /pb3 artclk /(hs) pb4 artic1 / pb5 artic2 / pb6 pb7 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 (hs) pe4 (hs) pe5 (hs) pe6 (hs) pe7 pa1 pa0 pc7 / ss / ain15 pc6 / sck / iccclk pc5 / mosi / ain14 pc4 / miso / iccdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b / ain13 pc0 / ocmp2_b / ain12 v ss_0 v dd_0 v ss_1 v dd_1 pa3 (hs) pa2 v dd _2 osc1 osc2 v ss _2 tli evd reset v pp / iccsel pa7 (hs) / scli pa6 (hs) / sdai pa5 (hs) pa4 (hs) pe3 pe2 pe1 / rdi pe0 / tdo (hs) 20ma high sink capability eix associated external interrupt vector st72321r/ar 9/178 pin description (contd) for external pin connection guidelines, refer to see electrical characteristics on page 135. legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.3v dd /0.7v dd with input trigger t t = ttl 0.8v / 2v with schmitt trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: C input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog C output: od = open drain 2) , pp = push-pull refer to i/o ports on page 45 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. table 1. device pin description pin n pin name type level port main function (after reset) alternate function input output input output float wpu int ana od pp 1 pe4 (hs) i/o c t hs x x x x port e4 2 pe5 (hs) i/o c t hs x x x x port e5 3 pe6 (hs) i/o c t hs x x x x port e6 4 pe7 (hs) i/o c t hs x x x x port e7 5 pb0/pwm3 i/o c t x ei 2 x x port b0 pwm output 3 6 pb1/pwm2 i/o c t x ei 2 x x port b1 pwm output 2 7 pb2/pwm1 i/o c t x ei 2 x x port b2 pwm output 1 8 pb3/pwm0 i/o c t x ei2 x x port b3 pwm output 0 9 pb4 (hs)/artclk i/o c t hs x ei3 x x port b4 pwm-art external clock 10 pb5 / artic1 i/o c t x ei3 x x port b5 pwm-art input capture 1 11 pb6 / artic2 i/o c t x ei3 x x port b6 pwm-art input capture 2 12 pb7 i/o c t x ei3 x x port b7 13 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 14 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 15 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 16 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 17 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 18 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 19 pd6/ain6 i/o c t x x x x x port d6 adc analog input 6 20 pd7/ain7 i/o c t x x x x x port d7 adc analog input 7 21 v aref i analog reference voltage for adc 22 v ssa s analog ground voltage 23 v dd_3 s digital main supply voltage st72321r/ar 10/178 24 v ss_3 s digital ground voltage 25 pf0/mco/ain8 i/o c t x ei1 x x port f0 main clock out (f osc /2) adc analog input 8 26 pf1 (hs)/beep i/o c t hs x ei1 x x port f1 beep signal output 27 pf2 (hs) i/o c t hs x ei1 x x port f2 28 pf3/ocmp2_a/ain9 i/o c t x x x x port f3 timer a output compare 2 adc analog input 9 29 pf4/ocmp1_a/ain10 i/o c t x x x x port f4 timer a output compare 1 adc analog input 10 30 pf5/icap2_a/ain11 i/o c t x x x x port f5 timer a input capture 2 adc analog input 11 31 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 32 pf7 (hs)/extclk_a i/o c t hs x x x x port f7 timer a external clock source 33 v dd_0 s digital main supply voltage 34 v ss_0 s digital ground voltage 35 pc0/ocmp2_b/ain12 i/o c t x x x x port c0 timer b output compare 2 adc analog input 12 36 pc1/ocmp1_b/ain13 i/o c t x x x x port c1 timer b output compare 1 adc analog input 13 37 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 38 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 39 pc4/miso/iccdata i/o c t x x x x port c4 spi master in / slave out data icc data input 40 pc5/mosi/ain14 i/o c t x x x x port c5 spi master out / slave in data adc analog input 14 41 pc6/sck/iccclk i/o c t x x x x port c6 spi serial clock icc clock out- put 42 pc7/ss /ain15 i/o c t x x x x port c7 spi slave se- lect (active low) adc analog input 15 43 pa0 i/o c t x ei0 x x port a0 44 pa1 i/o c t x ei0 x x port a1 45 pa2 i/o c t x ei0 x x port a2 46 pa3 (hs) i/o c t hs x ei0 x x port a3 47 v dd_1 s digital main supply voltage 48 v ss_1 s digital ground voltage 49 pa4 (hs) i/o c t hs x x x x port a4 50 pa5 (hs) i/o c t hs x x x x port a5 51 pa6 (hs)/sdai i/o c t hs x t port a6 i 2 c data 1) 52 pa7 (hs)/scli i/o c t hs x t port a7 i 2 c clock 1) pin n pin name type level port main function (after reset) alternate function input output input output float wpu int ana od pp st72321r/ar 11/178 notes : 1. in the interrupt input column, eix defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. in the open drain output column, t defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see see i/o ports on page 45. and section 12.8 i/o port pin character- istics for more details. 3. osc1 and osc2 pins connect a crystal/ceramic resonator, an rc oscillator, or an external source to the on-chip oscillator; see section 1 introduction and section 12.5 clock and timing charac- teristics for more details. 4. on the chip, each i/o port has 8 pads. pads that are not bonded to external pins are in input pull-up con- figuration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. 53 v pp / iccsel i must be tied low. in flash programming mode, this pin acts as the programming volt- age input v pp . see section 12.9.2 for more details. high voltage must not be applied to rom devices 54 reset i/o c t top priority non maskable interrupt. 55 evd external voltage detector 56 tli i c t x top level interrupt input pin 57 v ss_2 s digital ground voltage 58 osc2 3) i/o resonator oscillator inverter output or ca- pacitor input for rc oscillator 59 osc1 3) i external clock input or resonator oscillator inverter input or resistor input for rc oscilla- tor 60 v dd_2 s digital main supply voltage 61 pe0/tdo i/o c t x x x x port e0 sci transmit data out 62 pe1/rdi i/o c t x x x x port e1 sci receive data in 63 pe2 i/o c t x port e2 64 pe3 i/o c t x x x x port e3 pin n pin name type level port main function (after reset) alternate function input output input output float wpu int ana od pp st72321r/ar 12/178 3 register & memory map as shown in figure 3 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 2kbytes of ram and up to 60kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. figure 3. memory map 0000h ram program memory (60k, 48k or 32k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see table 2 ) 1000h ffdfh ffe0h ffffh (see table 8 ) 0880h reserved 087fh short addressing ram (zero page) 256 bytes stack 16-bit addressing ram 0100h 01ffh 0080h 0200h 00ffh or 087fh 32 kbytes 8000h 60 kbytes 48 kbytes ffffh 1000h 4000h (2048, 1536 or 1024 bytes) or 067fh or 047fh st72321r/ar 13/178 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 1) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d pddr pdddr pdor port d data register port d data direction register port d option register 00h 1) 00h 00h r/w r/w r/w 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h 1) 00h 00h r/w r/w 2) r/w 2) 000fh 0010h 0011h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h 1) 00h 00h r/w r/w r/w 0012h to 0017h reserved area (6 bytes) 0018h 0019h 001ah 001bh 001ch 001dh 001eh i 2 c i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c own address register 1 i 2 c own address register2 i 2 c data register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w 001fh 0020h reserved area (2 bytes) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h eicr external interrupt control register 00h r/w 0029h flash fcsr flash control/status register 00h r/w st72321r/ar 14/178 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh sicsr system integrity control/status register 000x 000x b r/w 002ch 002dh mcc mccsr mccbcr main clock control / status register main clock controller: beep control register 00h 00h r/w r/w 002eh to 0030h reserved area (3 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tacsr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved area (1 byte) 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbcsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00xx xxxxb xxh 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w address block register label register name reset status remarks st72321r/ar 15/178 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 0058h to 006fh reserved area (24 bytes) 0070h 0071h 0072h adc adccsr adcdrh adcdrl control/status register data high register data low register 00h xxh 0000 00xxb r/w read only read only 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh pwm art pwmdcr3 pwmdcr2 pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr articcsr articr1 articr2 pwm ar timer duty cycle register 3 pwm ar timer duty cycle register 2 pwm ar timer duty cycle register 1 pwm ar timer duty cycle register 0 pwm ar timer control register auto-reload timer control/status register auto-reload timer counter access register auto-reload timer auto-reload register ar timer input capture control/status reg. ar timer input capture register 1 ar timer input capture register 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only 007eh 007fh reserved area (2 bytes) address block register label register name reset status remarks st72321r/ar 16/178 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a byte-by-byte ba- sis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features n three flash programming modes: C insertion in a programming tool. in this mode, all sectors including option bytes can be pro- grammed or erased. C icp (in-circuit programming). in this mode, all sectors including option bytes can be pro- grammed or erased without removing the de- vice from the application board. C iap (in-application programming) in this mode, all sectors except sector 0, can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. n ict (in-circuit testing) for downloading and executing user application test patterns in ram n read-out protection against piracy n register access security system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see table 3 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 4 ). they are mapped in the upper part of the st7 addressing space so the reset and in- terrupt vectors are located in sector 0 (f000h- ffffh). table 3. sectors available in flash devices 4.3.1 read-out protection read-out protection, when selected, makes it im- possible to extract the memory content from the microcontroller, thus preventing piracy. even st cannot access the user code. in flash devices, this protection is removed by re- programming the option. in this case, the entire program memory is first automatically erased. read-out protection selection depends on the de- vice type: C in flash devices it is enabled and removed through the fmp_r bit in the option byte. C in rom devices it is enabled by mask option specified in the option list. figure 4. memory map and sector address flash size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k st72321r/ar 17/178 flash program memory (contd) 4.4 icc interface icc needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see figure 5 ). these pins are: C reset : device reset Cv ss : device power supply ground C iccclk: icc output serial clock pin C iccdata: icc input/output serial data pin C iccsel/v pp : programming voltage C osc1(or oscin): main clock input for exter- nal source (optional) Cv dd : application board power supply (option- al, see figure 5 , note 3) figure 5. typical icc interface notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icc session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. w hen using a classical rc network with r>1k or a reset man- agement ic with open drain output and pull-up re- sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 or os- cin pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator capability need to have osc2 grounded in this case. 5. in the application, when the reset pin is low, the iccclk pin must always be in pull-up or high impedance state. for instance, it must never be forced to ground or connected to an external pull- down. this is to avoid entering icc mode unex- pectedly during normal application operation. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable optional (see note 3) 10k w v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see notes 1 and 5 see note 2 application reset source application i/o (see note 4) st72321r/ar 18/178 flash program memory (contd) 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the spe- cific microcontroller device, the user needs only to implement the icp hardware interface on the ap- plication board (see figure 5 ). for more details on the pin locations, refer to the device pinout de- scription. 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci, usb or can interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase pro- tected to allow recovery in case errors occur dur- ing the programming operation. 4.6.1 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. for details on customizing flash programming methods and in-circuit test- ing, refer to the st7 flash programming refer- ence manual. table 4. flash control/status register address and reset value 70 00000000 address (hex.) register label 76543210 0029h fcsr reset value00000000 st72321r/ar 19/178 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features n enable executing 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n low power halt and wait modes n priority maskable hardware interrupts n non-maskable software/hardware interrupts 5.3 cpu registers the 6 cpu registers shown in figure 6 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 6. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value st72321r/ar 20/178 central processing unit (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. its a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 st72321r/ar 21/178 central processing unit (contd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 7 ). since the stack is 256 bytes deep, the 8 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 7 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 7. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h st72321r/ar 22/178 6 supply, reset and clock management the device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 9 . for more details, refer to dedicated parametric section. main features n optional pll for multiplying the frequency by 2 (not to be used with internal rc oscillator) n reset sequence manager (rsm) n multi-oscillator clock management (mo) C 5 crystal/ceramic resonator oscillators C 1 external rc oscillator C 1 internal rc oscillator n system integrity management (si) C main supply low voltage detection (lvd) C auxiliary voltage detector (avd) with interrupt capability for monitoring the main supply or the evd pin C clock security system (css) with clock filter and backup safe oscillator (enabled by op- tion byte) 6.1 phase locked loop if the clock frequency input to the pll is in the range 2 to 4 mhz, the pll can be used to multiply the frequency by two to obtain an f osc2 of 4 to 8 mhz. the pll is enabled by option byte. if the pll is disabled, then f osc2 = f osc /2. caution: the pll is not recommended for appli- cations where timing accuracy is required. see pll characteristics on page 149. figure 8. pll block diagram figure 9. clock, reset and supply block diagram 0 1 pll option bit pll x 2 f osc2 / 2 f osc low voltage detector (lvd) f osc2 auxiliary voltage detector (avd) multi- oscillator (mo) osc1 reset v ss evd v dd reset sequence manager (rsm) clock filter safe osc clock security system (css) osc2 main clock css interrupt request avd interrupt request controller pll system integrity management watchdog sicsr timer (wdg) with realtime clock (mcc/rtc) avd avd avd lvd rf css ie ie css d wdg rf 0 1 f osc f osc2 (option) 0 sf f cpu st72321r/ar 23/178 6.2 multi-oscillator (mo) the main clock of the st7 can be generated by four different source types coming from the multi- oscillator block: n an external source n 4 crystal or ceramic resonator oscillators n an external rc oscillator n an internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 5 . refer to the electrical characteristics section for more details. external clock source in this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. crystal/ceramic oscillators this family of oscillators has the advantage of pro- ducing a very accurate rate on the main clock of the st7. the selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 14.1 on page 170 for more details on the frequency ranges). in this mode of the multi- oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscil- lator pins in order to minimize output distortion and start-up stabilization time. the loading capaci- tance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. external rc oscillator this oscillator allows a low cost solution for the main clock of the st7 using only an external resis- tor and an external capacitor. the frequency of the external rc oscillator (in the range of some mhz.) is fixed by the resistor and the capacitor values. consequently in this mo mode, the accuracy of the clock is directly linked to the accuracy of the discrete components. the corresponding formula is f osc =5/(r ex c ex ) . internal rc oscillator the internal rc oscillator mode is based on the same principle as the external rc oscillator includ- ing the resistance and the capacitance of the de- vice. this mode is the most cost effective one with the drawback of a lower frequency accuracy. its frequency is in the range of several mhz. in this mode, the two oscillator pins have to be tied to ground. table 5. st7 clock sources hardware configuration external clock crystal/ceramic resonators external rc oscillator internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7 c ex r ex osc1 osc2 st7 st72321r/ar 24/178 6.3 reset sequence manager (rsm) 6.3.1 introduction the reset sequence manager includes three re- set sources as shown in figure 11 : n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 10 : n active phase depending on the reset source n 256 or 4096 cpu clock cycle delay (selected by option byte) n reset vector fetch the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 14.1 on page 170 ). the reset vector fetch phase duration is 2 clock cycles. figure 10. reset sequence phases 6.3.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see control pin characteristics on page 159 for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 12 ). this de- tection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 11. reset block diagram reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter st72321r/ar 25/178 reset sequence manager (contd) the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. if the external reset pulse is shorter than t w(rstl)out (see short ext. reset in figure 12 ), the signal on the reset pin may be stretched. other- wise the delay will not be applied (see long ext. reset in figure 12 ). starting from the external re- set pulse recognition, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 6.3.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. (see operating conditions on page 137 ) a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. 6.3.4 internal low voltage detector (lvd) reset two different reset s equences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop r eset the device reset pin acts as an output that is pulled low when v dd st72321r/ar 27/178 system integrity management (contd) 6.4.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main sup- ply or the external evd pin voltage level (v evd ). the v it- reference value for falling voltage is lower than the v it+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly read- able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution : the avd function is active only if the lvd is enabled through the option byte. 6.4.2.1 monitoring the v dd main supply this mode is selected by clearing the avds bit in the sicsr register. the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 14.1 on page 170 ). if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit toggles). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon- troller. see figure 14 . the interrupt on the rising edge is used to inform the application that the v dd warning state is over. if the voltage rise time t rv is less than 256 or 4096 cpu cycles (depending on the reset delay select- ed by option byte), no avd interrupt will be gener- ated when v it+(avd) is reached. if t rv is greater than 256 or 4096 cycles then: C if the avd interrupt is enabled before the v it+(avd) threshold is reached, then 2 avd inter- rupts will be received: the first when the avdie bit is set, and the second when the threshold is reached. C if the avd interrupt is enabled after the v it+(avd) threshold is reached then only one avd interrupt will occur. figure 14. using the avd to monitor v dd (avds bit=0) v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 1 t rv voltage rise time st72321r/ar 28/178 system integrity management (contd) 6.4.2.2 monitoring a voltage on the evd pin this mode is selected by setting the avds bit in the sicsr register. the avd circuitry can generate an interrupt when the avdie bit of the sicsr register is set. this in- terrupt is generated on the rising and falling edges of the comparator output. this means it is generat- ed when either one of these two events occur: Cv evd rises up to v it+(evd) Cv evd falls down to v it-(evd) the evd function is illustrated in figure 15 . for more details, refer to the electrical character- istics section. figure 15. using the voltage detector to monitor the evd pin (avds bit=1) v evd v it+(evd) v it-(evd) avdf 0 0 1 if avdie = 1 v hyst avd interrupt request interrupt process interrupt process st72321r/ar 29/178 system integrity management (contd) 6.4.3 clock security system (css) the clock security system (css) protects the st7 against breakdowns, spikes and overfrequen- cies occurring on the main clock source (f osc ). it is based on a clock filter and a clock detection con- trol with an internal safe oscillator (f sfosc ). 6.4.3.1 clock filter control the pll has an integrated glitch filtering capability making it possible to protect the internal clock from overfrequencies created by individual spikes. this feature is available only when the pll is enabled. if glitches occur on f osc (for example, due to loose connection or noise), the css filters these auto- matically, so the internal cpu frequency (f cpu ) continues deliver a glitch-free signal (s ee figure 16) . 6.4.3.2 clock detection control if the clock signal disappears (due to a broken or disconnected resonator...), the safe oscillator de- livers a low frequency clock signal (f sfosc ) which allows the st7 to perform some rescue opera- tions. automatically, the st7 clock source switches back from the safe oscillator (f sfosc ) if the main clock source (f osc ) recovers. when the internal clock (f cpu ) is driven by the safe oscillator (f sfosc ), the application software is noti- fied by hardware setting the cssd bit in the sic- sr register. an interrupt can be generated if the cssie bit has been previously set. these two bits are described in the sicsr register description. 6.4.4 low power modes 6.4.4.1 interrupts the css or avd interrupt events generate an in- terrupt if the corresponding enable control bit (cssie or avdie) is set and the interrupt mask in the cc register is reset (rim instruction). figure 16. clock filter function mode description wait no effect on si. css and avd interrupts cause the device to exit from wait mode. halt the crsr register is frozen. the css (including the safe oscillator) is disabled until halt mode is exited. the previous css configuration resumes when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. interrupt event event flag enable control bit exit from wait exit from halt css event detection (safe oscillator acti- vated as main clock) cssd cssie yes no avd event avdf avdie yes no f osc2 f cpu f osc2 f cpu f sfosc pll on clock filter function clock detection function st72321r/ar 30/178 system integrity management (contd) 6.4.5 register description system integrity (si) control/status register (sicsr) read/write reset value: 000x 000x (00h) bit 7 = avds voltage detection selection this bit is set and cleared by software. voltage de- tection is available only if the lvd is enabled by option byte. 0: voltage detection on v dd supply 1: voltage detection on evd pin bit 6 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt informa- tion is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled bit 5 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen- erated when the avdf bit changes value. refer to figure 14 and to section 6.4.2.1 for additional de- tails. 0: v dd or v evd over v it+(avd) threshold 1: v dd or v evd under v it-(avd) threshold bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 3 = reserved, must be kept cleared. bit 2 = cssie clock security syst . interrupt enable this bit enables the interrupt when a disturbance is detected by the clock security system (cssd bit set). it is set and cleared by software. 0: clock security system interrupt disabled 1: clock security system interrupt enabled when the css is disabled by option byte, the cssie bit has no effect. bit 1 = cssd clock security system detection this bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (f osc ). it is set by hardware and cleared by reading the sicsr register when the original oscil- lator recovers. 0: safe oscillator is not active 1: safe oscillator has been activated when the css is disabled by option byte, the cssd bit value is forced to 0. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was generat- ed by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. caution: when the lvd is not activated with the associated option byte, the wdgrf flag can not be used in the application. 70 avd s avd ie avd f lvd rf 0 css ie css d wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x st72321r/ar 31/178 7 interrupts 7.1 introduction the st7 enhanced interrupt management pro- vides the following features: n hardware interrupts n software interrupt (trap) n nested or concurrent interrupt management with flexible interrupt priority and level management: C up to 4 software programmable nesting levels C up to 16 interrupt vectors fixed by hardware C 3 non maskable events: tli, reset, trap this interrupt management is based on: C bit 5 and bit 3 of the cpu cc register (i1:0), C interrupt software priority registers (isprx), C fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with the standard (not nest- ed) st7 interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see table 6 ). the process- ing flow is shown in figure 17 when an interrupt request has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the previous level will resume. table 6. interrupt software priority levels figure 17. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 iret restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset trap pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt st72321r/ar 32/178 interrupts (contd) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: C the highest software priority interrupt is serviced, C if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 18 describes this decision process. figure 18. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : tli, reset and trap are non maskable and they can be considered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, tli, trap) and the maskable type (ex- ternal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 17 ). after stacking the pc, x, a and cc registers (except for reset), the corres ponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. n tli (top level hardware interrupt) this hardware interrupt occurs when a specific edge is detected on the dedicated tli pin. it will be serviced according to the flowchart in figure 17 as a trap. caution : a trap instruction must not be used in a tli service routine. n trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart in figure 17 . caution: trap can be interrupted by a tli. n reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. n external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitiv- ity is software selectable through the external in- terrupt control register (eicr). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. n peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the interrupt mapping table. a peripheral inter- rupt occurs when a specific flag is set in the pe- ripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced st72321r/ar 33/178 interrupts (contd) 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column exit from halt in interrupt mapping table). when several pending interrupts are present while exit- ing halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision proc- ess shown in figure 18 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent & nested management the following figure 19 and figure 20 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 20 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 19. concurrent interrupt management figure 20. nested interrupt management main it4 it2 it1 trap it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 trap it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 trap main it0 it2 it1 it4 trap it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes st72321r/ar 34/178 interrupts (contd) 7.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see interrupt dedicated instruction set table). *note : tli, trap and reset events are non maskable sources and can interrupt a level 3 pro- gram. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. C each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. C each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. C level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the tli, reset, and trap vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the tli can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits st72321r/ar 35/178 interrupts (contd) table 7. dedicated interrupt instruction set note : during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 (level 3) i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 st72321r/ar 36/178 interrupts (contd) table 8. interrupt mapping notes: 1. valid for halt and active-halt modes except for the mcc/rtc or css interrupt source which exits from active-halt mode only. 7.6 external interrupts 7.6.1 i/o port interrupt sensitivity the external interrupt sensitivity is controlled by the ipa, ipb and isxx bits of the eicr register ( figure 21 ). this control allows to have up to 4 fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: n falling edge n rising edge n falling and rising edge n falling edge and low level n rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). this means that interrupts must be disabled before changing sensitivity. the pending interrupts are cleared by writing a dif- ferent value in the isx[1:0], ipa or ipb bits of the eicr. n source block description register label priority order exit from halt 1) address vector reset reset n/a yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 tli external top level interrupt eicr yes fffah-fffbh 1 mcc/rtc css main clock controller time base interrupt safe oscillator activation interrupt mccsr sicsr higher priority yes fff8h-fff9h 2 ei0 external interrupt port a3..0 n/a yes fff6h-fff7h 3 ei1 external interrupt port f2..0 yes fff4h-fff5h 4 ei2 external interrupt port b3..0 yes fff2h-fff3h 5 ei3 external interrupt port b7..4 yes fff0h-fff1h 6 not used ffeeh-ffefh 7 spi spi peripheral interrupts spicsr yes ffech-ffedh 8 timer a timer a peripheral interrupts tasr no ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr no ffe8h-ffe9h 10 sci sci peripheral interrupts scisr lower priority no ffe6h-ffe7h 11 avd auxiliary voltage detector interrupt sicsr no ffe4h-ffe5h 12 i2c i2c peripheral interrupts (see periph) no ffe2h-ffe3h 13 pwm art pwm art interrupt artcsr yes ffe0h-ffe1h st72321r/ar 37/178 interrupts (contd) figure 21. external interrupt control bits is10 is11 eicr sensitivity control pbor.3 pbddr.3 ipb bit pb3 ei2 interrupt source port b [3:0] interrupts pb3 pb2 pb1 pb0 is10 is11 eicr sensitivity control pbor.7 pbddr.7 pb7 ei3 interrupt source port b [7:4] interrupts pb7 pb6 pb5 pb4 is20 is21 eicr sensitivity control paor.3 paddr.3 ipa bit pa3 ei0 interrupt source port a [3:0] interrupts pa3 pa2 pa1 pa0 is20 is21 eicr sensitivity control pfor.2 pfddr.2 pf2 ei1 interrupt source port f [2:0] interrupts pf2 pf1 pf0 st72321r/ar 38/178 7.7 external interrupt control register (eicr) read/write reset value: 0000 0000 (00h) bit 7:6 = is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: - ei2 (port b3..0) - ei3 (port b7..4) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 5 = ipb interrupt polarity for port b this bit is used to invert the sensitivity of the port b [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion bit 4:3 = is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: - ei0 (port a3..0) - ei1 (port f2..0) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 2 = ipa interrupt polarity for port a this bit is used to invert the sensitivity of the port a [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion bit 1 = tlis tli sensitivity this bit allows to toggle the tli edge sensitivity. it can be set and cleared by software only when tlie bit is cleared. 0: falling edge 1: rising edge bit 0 = tlie tli enable this bit allows to enable or disable the tli capabil- ity on the dedicated pin. it is set and cleared by software. 0: tli disabled 1: tli enabled note : a parasitic interrupt can be generated when 70 is11 is10 ipb is21 is20 ipa tlis tlie is11 is10 external interrupt sensitivity ipb bit =0 ipb bit =1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is11 is10 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity ipa bit =0 ipa bit =1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge st72321r/ar 39/178 interrupts (contd) table 9. nested interrupts register map and reset values address (hex.) register label 76543210 0024h ispr0 reset value ei1 ei0 mcc + si tli i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0025h ispr1 reset value spi ei3 ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 reset value avd sci timer b timer a i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value1111 pwmart i2c i1_13 1 i0_13 1 i1_12 1 i0_12 1 0028h eicr reset value is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 0 tlis 0 tlie 0 st72321r/ar 40/178 8 power saving modes 8.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 22 ): slow, wait (slow wait), ac- tive halt and halt. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. figure 22. power saving mode transitions 8.2 slow mode this mode has two targets: C to reduce power consumption by decreasing the internal clock in the device, C to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and pe- ripherals are clocked at this lower frequency (f cpu ). note : slow-wait mode is activated when enter- ing the wait mode while the device is already in slow mode. figure 23. slow mode clock transitions power consumption wait slow run active halt high low slow wait halt 00 01 sms cp1:0 f cpu new slow normal run mode mccsr frequency request request f osc2 f osc2 /2 f osc2 /4 f osc2 st72321r/ar 41/178 power saving modes (contd) 8.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to 10, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 24 . figure 24. wait mode flow-chart note: 1. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx 1) on 256 or 4096 cpu clock cycle delay st72321r/ar 42/178 power saving modes (contd) 8.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the halt instruc- tion. the decision to enter either in active-halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in mccsr register). 8.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the halt in- struction when the oie bit of the main clock con- troller status register (mccsr) is set (see section 10.2 on page 56 for more details on the mccsr register). the mcu can exit active-halt mode on recep- tion of either an mcc/rtc interrupt, a specific in- terrupt (see table 8, interrupt mapping, on page 36 ) or a reset. when exiting active- halt mode by means of an interrupt, no 256 or 4096 cpu cycle delay occurs. the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 26 ). when entering active-halt mode, the i[1:0] bits in the cc register are forced to 10b to enable in- terrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillator and its associated counter (mcc/rtc) are run- ning to keep a wake-up time base. all other periph- erals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). the safeguard against staying locked in active- halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capability of one of the oscillators is selected (mccsr.oie bit set), entering active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. caution: when exiting active-halt mode fol- lowing an interrupt, oie bit of mccsr register must not be cleared before t delay after the inter- rupt occurs (t delay = 256 or 4096 t cpu delay de- pending on option byte). otherwise, the st7 en- ters halt mode for the remaining t delay period. figure 25. active-halt timing overview figure 26. active-halt mode flow-chart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripheral clocked with an external clock source can still be active. 3. only the mcc/rtc interrupt and some specific interrupts can exit the mcu from active-halt mode (such as external interrupt). refer to table 8, interrupt mapping, on page 36 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and restored when the cc register is popped. mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode halt run run 256 or 4096 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [mccsr.oie=1] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256or4096cpuclock cycle delay (mccsr.oie=1) st72321r/ar 43/178 power saving modes (contd) 8.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the halt instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 10.2 on page 56 for more de- tails on the mccsr register). the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 8, interrupt mapping, on page 36 ) or a reset. w hen exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see fig- ure 28 ). when entering halt mode, the i[1:0] bits in the cc register are forced to 10bto enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of watchdog operation with halt mode is configured by the wdghalt op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see section 14.1 on page 170 for more details). figure 27. halt timing overview figure 28. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 8, interrupt mapping, on page 36 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie=0] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 (mccsr.oie=0) cycle st72321r/ar 44/178 power saving modes (contd) 8.4.2.1 halt mode recommendations C make sure that an external event is available to wake up the microcontroller from halt mode. C when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as input pull-up with interrupt before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. C for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. C the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. C as the halt instruction clears the interrupt mask in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits be- fore executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corre- sponding to the wake-up event (reset or external interrupt). st72321r/ar 45/178 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C external interrupt generation C alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 functional description each port has 2 main registers: C data register (dr) C data direction register (ddr) and one optional register: C option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 29 9.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. 3. do not use read/modify/write instructions (bset or bres) to modify the dr register external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 9.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 9.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pull open-drain 0v ss vss 1v dd floating st72321r/ar 46/178 i/o ports (contd) figure 29. i/o port general block diagram table 10. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) external source (ei x ) interrupt cmos schmitt trigger register access st72321r/ar 47/178 i/o ports (contd) table 11. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) condition pad v dd r pu external interrupt data bus pull-up interrupt dr register access w r source (ei x ) dr register condition alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports st72321r/ar 48/178 i/o ports (contd) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 9.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 30 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 30. interrupt i/o port state transitions 9.4 low power modes 9.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or st72321r/ar 49/178 i/o ports (contd) 9.5.1 i/o port implementation the i/o port register configurations are summa- rised as follows. standard ports pa5:4, pc7:0, pd7:0, pe7:34, pe1:0, pf7:3, interrupt ports pa2:0, pb6:5, pb4, pb2:0, pf1:0 (with pull-up) pa3, pb7, pb3, pf2 (without pull-up) true open drain ports pa7:6 pull-up input port pe2 table 12. port configuration mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr floating input 0 open drain (high sink ports) 1 mode pull-up input port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:6 floating true open-drain pa5:4 floating pull-up open drain push-pull pa3 floating floating interrupt open drain push-pull pa2:0 floating pull-up interrupt open drain push-pull port b pb7, pb3 floating floating interrupt open drain push-pull pb6:5, pb4, pb2:0 floating pull-up interrupt open drain push-pull port c pc7:0 floating pull-up open drain push-pull port d pd7:0 floating pull-up open drain push-pull port e pe7:3, pe1:0 floating pull-up open drain push-pull pe2 pull-up input only port f pf7:3 floating pull-up open drain push-pull pf2 floating floating interrupt open drain push-pull pf1:0 floating pull-up interrupt open drain push-pull st72321r/ar 50/178 i/o ports (contd) table 13. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor st72321r/ar 51/178 10 on-chip peripherals 10.1 watchdog timer (wdg) 10.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 10.1.2 main features n programmable timer n programmable reset n reset (if watchdog activated) when the t6 bit reaches zero n optional reset on halt instruction (configurable by option byte) n hardware watchdog selectable by option byte 10.1.3 functional description the counter value stored in the watchdog control register (wdgcr bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the wdgcr register at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the wdgcr register must be be- tween ffh and c0h: C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 32. ap- proximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writ- ing to the wdgcr register (see figure 33 ). following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. figure 31. watchdog block diagram reset wdga 6-bit downcounter (cnt) f osc2 t6 t0 wdg prescaler watchdog control register (wdgcr) div 4 t1 t2 t3 t4 t5 12-bit mcc rtc counter msb lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register) st72321r/ar 52/178 watchdog timer (contd) 10.1.4 how to program the watchdog timeout figure 32 shows the linear relationship between the 6-bit value to be loaded in the watchdog coun- ter (cnt) and the resulting timeout duration in mil- liseconds. this can be used for a quick calculation without taking the timing variations into account. if more precision is needed, use the formulae in fig- ure 33 . caution: when writing to the wdgcr register, al- ways write 1 in the t6 bit to avoid generating an immediate reset. figure 32. approximate timeout duration cnt value (hex.) watchdog timeout (ms) @ 8 mhz. f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 st72321r/ar 53/178 watchdog timer (contd) figure 33. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example: with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cn t 4cnt msb ---------------- - C ? ?? 192 ls b + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 c nt t osc2 + = t max t max0 16384 c nt 4cnt msb ---------------- - C ? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = st72321r/ar 54/178 watchdog timer (contd) 10.1.5 low power modes 10.1.6 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description. 10.1.7 using halt mode with the wdg (wdghalt option) the following recommendation applies if halt mode is used when the watchdog is enabled. C before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. 10.1.8 interrupts none. 10.1.9 register description control register (wdgcr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit counter (msb to lsb). these bits contain the value of the watchdog counter. it is decremented every 16384 f osc2 cy- cles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). mode description slow no effect on watchdog. wait no effect on watchdog. halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watch- dog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the mcu receives an external inter- rupt or a reset. if an external interrupt is received, the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for applica- tion recommendations see section 10.1.7 below. 0 1 a reset is generated. 1x no reset is generated. the mcu enters active halt mode. the watchdog counter is not decremented. it stop counting. when the mcu receives an oscillator interrupt or external interrupt, the watchdog restarts counting im- mediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks. 70 wdga t6 t5 t4 t3 t2 t1 t0 st72321r/ar 55/178 table 14. watchdog timer register map and reset values address (hex.) register label 76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 st72321r/ar 56/178 10.2 main clock controller with real time clock and beeper (mcc/rtc) the main clock controller consists of three differ- ent functions: n a programmable cpu clock prescaler n a clock-out signal to supply external devices n a real time clock timer with interrupt capability each function can be used independently and si- multaneously. 10.2.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal periph- erals. it manages slow power saving mode (see section 8.2 slow mode for more details). the prescaler selects the f cpu main clock frequen- cy and is controlled by three bits in the mccsr register: cp[1:0] and sms. 10.2.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f osc2 clock to drive external devices. it is controlled by the mco bit in the mccsr register. caution : when selected, the clock out pin sus- pends the clock during active-halt mode. 10.2.3 real time clock timer (rtc) the counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. four different time bases depend- ing directly on f osc2 are available. the whole functionality is controlled by four bits of the mcc- sr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 8.4 ac- tive-halt and halt modes for more details. 10.2.4 beeper the beep function is controlled by the mccbcr register. it can output three selectable frequencies on the beep pin (i/o port alternate function). figure 34. main clock controller (mcc/rtc) block diagram div 2, 4, 8, 16 mcc/rtc interrupt sms cp1 cp0 tb1 tb0 oie oif cpu clock mccsr 12-bit mcc rtc counter to cpu and peripherals f osc2 f cpu mco mco bc1 bc0 mccbcr beep generator beep signal 1 0 to watchdog timer div 64 st72321r/ar 57/178 main clock controller with real time clock (contd) 10.2.5 low power modes 10.2.6 interrupts the mcc/rtc interrupt event generates an inter- rupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). note : the mcc/rtc interrupt wakes up the mcu from active-halt mode, not from halt mode. 10.2.7 register description mcc control/status register (mccsr) read/write reset value: 0000 0000 (00h ) bit 7 = mco main clock out selection this bit enables the mco alternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) note : to reduce power consumption, the mco function is not active in active-halt mode. bit 6:5 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 4 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc2 1: slow mode. f cpu is given by cp1, cp0 see section 8.2 slow mode and section 10.2 main clock controller with real time clock and beeper (mcc/rtc) for more de- tails. bit 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active- halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the device to exit from wait mode. active- halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with exit from halt capability. interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no 1) 70 mco cp1 cp0 sms tb1 tb0 oie oif f cpu in slow mode cp1 cp0 f osc2 / 2 0 0 f osc2 / 4 0 1 f osc2 / 8 1 0 f osc2 / 16 1 1 counter prescaler time base tb1 tb0 f osc2 =4mhz f osc2 =8mhz 16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 1 st72321r/ar 58/178 main clock controller with real time clock (contd) bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the mccsr register. it indicates when set that the main oscillator has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. mcc beep control register (mccbcr) read/write reset value: 0000 0000 (00h) bit 7:2 = reserved, must be kept cleared. bit 1:0 = bc[1:0] beep control these 2 bits select the pf1 pin beep capability. the beep output signal is available in active- halt mode but has to be disabled to reduce the consumption. table 15. main clock controller register map and reset values 70 000000bc1bc0 bc1 bc0 beep mode with f osc2 =8mhz 00 off 0 1 ~2-khz output beep signal ~50% duty cycle 1 0 ~1-khz 1 1 ~500-hz address (hex.) register label 76543210 002bh sicsr reset value vds 0 vdie 0 vdf 0 lvdrf x0 cfie 0 cssd 0 wdgrf x 002ch mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 002dh mccbcr reset value000000 bc1 0 bc0 0 st72321r/ar 59/178 10.3 pwm auto-reload timer (art) 10.3.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. these resources allow five possible operating modes: C generation of up to 4 independent pwm signals C output compare and time base interrupt C up to two input capture functions C external event detector C up to two external interrupt sources the three first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 35. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port function alternate ocrx compare register programmable prescaler 8-bit counter (car register) arr register icrx register load opx polarity control oex pwmcr mux f cpu dcrx register load f counter artclk f ext articx icfx icsx iccsr load icx interrupt iciex input capture control st72321r/ar 60/178 pwm auto-reload timer (contd) 10.3.2 functional description counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (artcar). when a counter overflow occurs, the counter is automatically reloaded with the contents of the artarr register (the prescaler is not affected). counter clock and prescaler the counter clock frequency is given by: f counter = f input / 2 cc[2:0] the timer counters input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (artcsr). thus the division factor of the prescal- er can be set to 2 n (where n = 0, 1,..7). this f input frequency source is selected through the excl bit of the artcsr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the artcsr register. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. counter and prescaler initialization after reset, the counter and the prescaler are cleared and f input = f cpu . the counter can be initialized by: C writing to the artarr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the artcsr reg- ister. C writing to the artcar counter access register, in both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. direct access to the prescaler is not possible. output compare control the timer compare function is based on four differ- ent comparisons with the counter (one for each pwmx output). each comparison is made be- tween the counter value and an output compare register (ocrx) value. this ocrx register can not be accessed directly, it is loaded from the duty cy- cle register (pwmdcrx) at each overflow of the counter. this double buffering method avoids glitch gener- ation when changing the duty cycle on the fly. figure 36. output compare control counter fdh feh ffh fdh feh ffh fdh feh artarr=fdh f counter ocrx pwmdcrx fdh feh fdh feh ffh pwmx st72321r/ar 61/178 pwm auto-reload timer (contd) independent pwm signal generation this mode allows up to four pulse width modulat- ed signals to be generated on the pwmx output pins with minimum core processing overhead. this function is stopped during halt mode. each pwmx output signal can be selected inde- pendently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as out- put push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the artarr register value. f pwm = f counter / (256 - artarr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be noted that the reload values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the artarr reg- ister. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - artarr) note : to get the maximum resolution (1/256), the artarr register must be 0. with this maximum resolution, 0% and 100% can be obtained by changing the polarity. figure 37. pwm auto-reload timer function figure 38. pwm signal from 0% to 100% duty cycle duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (artarr) (pwmdcrx) with oex=1 and opx=1 counter counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh artarr=fdh f counter st72321r/ar 62/178 pwm auto-reload timer (contd) output compare and time base interrupt on overflow, the ovf flag of the artcsr register is set and an overflow interrupt request is generat- ed if the overflow interrupt enable bit, oie, in the artcsr register, is set. the ovf flag must be re- set by the user software. this interrupt can be used as a time base in the application. external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the artarr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - artarr when entering halt mode while f ext is selected, all the timer control registers are frozen but the counter continues to increment. if the oie bit is set, the next overflow of the counter will generate an interrupt which wakes up the mcu. figure 39. external event detector example (3 counts) counter t fdh feh ffh fdh ovf artcsr read interrupt artarr=fdh f ext =f counter feh ffh fdh if oie=1 interrupt if oie=1 artcsr read st72321r/ar 63/178 pwm auto-reload timer (contd) input capture function this mode allows the measurement of external signal pulse widths through articrx registers. each input capture can generate an interrupt inde- pendently on a selected input signal transition. this event is flagged by a set of the corresponding cfx bits of the input capture control/status regis- ter (articcsr). these input capture interrupts are enabled through the ciex bits of the articcsr register. the active transition (falling or rising edge) is soft- ware programmable through the csx bits of the articcsr register. the read only input capture registers (articrx) are used to latch the auto-reload counter value when a transition is detected on the articx pin (cfx bit set in articcsr register). after fetching the interrupt vector, the cfx flags can be read to identify the interrupt source. note : after a capture detection, data transfer in the articrx register is inhibited until it is read (clearing the cfx bit). the timer interrupt remains pending while the cfx flag is set when the interrupt is enabled (ciex bit set). this means, the articrx register has to be read at each capture event to clear the cfx flag. the timing resolution is given by auto-reload coun- ter cycle time (1/f counter ). note: during halt mode, if both input capture and external clock are enabled, the articrx reg- ister value is not guaranteed if the input capture pin and the external clock change simultaneously. external interrupt capability this mode allows the input capture capabilities to be used as external interrupt sources. the inter- rupts are generated on the edge of the articx signal. the edge sensitivity of the external interrupts is programmable (csx bit of articcsr register) and they are independently enabled through ciex bits of the articcsr register. after fetching the interrupt vector, the cfx flags can be read to iden- tify the interrupt source. during halt mode, the external interrupts can be used to wake up the micro (if the ciex bit is set). figure 40. input capture timing diagram 04h counter t 01h f counter xxh 02h 03h 05h 06h 07h 04h articx pin cfx flag icrx register interrupt st72321r/ar 64/178 pwm auto-reload timer (contd) 10.3.3 register description control / status register (artcsr) read/write reset value: 0000 0000 (00h) bit 7 = excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock. 1: external clock. bit 6:4 = cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input . bit 3 = tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen). 1: counter running. bit 2 = fcrl force counter re-load this bit is write-only and any attempt to read it will yield a logical zero. when set, it causes the contents of artarr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. bit 1 = oie overflow interrupt enable this bit is set and cleared by software. it allows to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable. 1: overflow interrupt enable. bit 0 = ovf overflow flag this bit is set by hardware and cleared by software reading the artcsr register. it indicates the tran- sition of the counter from ffh to the artarr val- ue . 0: new transition not yet reached 1: transition reached counter access register (artcar) read/write reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] counter access data these bits can be set and cleared either by hard- ware or by software. the artcar register is used to read or write the auto-reload counter on the fly (while it is counting). auto-reload register (artarr) read/write reset value: 0000 0000 (00h) bit 7:0 = ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is au- tomatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register has two pwm management func- tions: C adjusting the pwm frequency C setting the pwm duty cycle resolution pwm frequency vs. resolution: 70 excl cc2 cc1 cc0 tce fcrl oie ovf f counter with f input =8 mhz cc2 cc1 cc0 f input f input / 2 f input / 4 f input / 8 f input / 16 f input / 32 f input / 64 f input / 128 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 70 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 70 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 artarr value resolution f pwm min max 0 8-bit ~0.244-khz 31.25-khz [ 0..127 ] > 7-bit ~0.244-khz 62.5-khz [ 128..191 ] > 6-bit ~0.488-khz 125-khz [ 192..223 ] > 5-bit ~0.977-khz 250-khz [ 224..239 ] > 4-bit ~1.953-khz 500-khz st72321r/ar 65/178 pwm auto-reload timer (contd) pwm control register (pwmcr) read/write reset value: 0000 0000 (00h) bit 7:4 = oe[3:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels inde- pendently acting on the corresponding i/o pin. 0: pwm output disabled. 1: pwm output enabled. bit 3:0 = op[3:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the four pwm output signals. note : when an opx bit is modified, the pwmx out- put signal polarity is immediately reversed. duty cycle registers (pwmdcrx) read/write reset value: 0000 0000 (00h) bit 7:0 = dc[7:0] duty cycle data these bits are set and cleared by software. a pwmdcrx register is associated with the ocrx register of each pwm channel to determine the second edge location of the pwm signal (the first edge location is common to all channels and given by the artarr register). these pwmdcr regis- ters allow the duty cycle to be set independently for each pwm channel. 70 oe3oe2oe1oe0op3op2op1op0 pwmx output level opx counter <= ocrx counter > ocrx 100 011 70 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 st72321r/ar 66/178 pwm auto-reload timer (contd) input capture control / status register (articcsr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved, always read as 0. bit 5:4 = cs[2:1] capture sensitivity these bits are set and cleared by software. they determine the trigger event polarity on the corre- sponding input capture channel. 0: falling edge triggers capture on channel x. 1: rising edge triggers capture on channel x. bit 3:2 = cie[2:1] capture interrupt enable these bits are set and cleared by software. they enable or disable the input capture channel inter- rupts independently. 0: input capture channel x interrupt disabled. 1: input capture channel x interrupt enabled. bit 1:0 = cf[2:1] capture flag these bits are set by hardware and cleared by software reading the corresponding articrx reg- ister. each cfx bit indicates that an input capture x has occurred. 0: no input capture on channel x. 1: an input capture has occured on channel x. input capture registers (articrx) read only reset value: 0000 0000 (00h) bit 7:0 = ic[7:0] input capture data these read only bits are set and cleared by hard- ware. an articrx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event. 70 0 0 cs2 cs1 cie2 cie1 cf2 cf1 70 ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 st72321r/ar 67/178 pwm auto-reload timer (contd) table 16. pwm auto-reload timer register map and reset values address (hex.) register label 76543210 0073h pwmdcr3 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0074h pwmdcr2 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0075h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0076h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0077h pwmcr reset value oe3 0 oe2 0 oe1 0 oe0 0 op3 0 op2 0 op1 0 op0 0 0078h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 rie 0 ovf 0 0079h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 007ah artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 007bh articcsr reset value 00 cs2 0 cs1 0 cie2 0 cie1 0 cf2 0 cf1 0 007ch articr1 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 007dh articr2 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 st72321r/ar 68/178 10.4 16-bit timer 10.4.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 10.4.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n 1 or 2 output compare functions each with: C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n 1 or 2 input capture functions each with: C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n reduced power mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 41 . *note: some timer pins may not available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be 1. 10.4.3 functional description 10.4.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): C counter high register (chr) is the most sig- nificant byte (ms byte). C counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) C alternate counter high register (achr) is the most significant byte (ms byte). C alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 17 clock control bits . the value in the counter register re- peats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. st72321r/ar 69/178 16-bit timer (contd) figure 41. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) csr st72321r/ar 70/178 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set and C i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 10.4.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronized with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte st72321r/ar 71/178 16-bit timer (contd) figure 42. counter timing diagram, internal clock divided by 2 figure 43. counter timing diagram, internal clock divided by 4 figure 44. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 st72321r/ar 72/178 16-bit timer (contd) 10.4.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected on the icap i pin (see figure 5). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function select the follow- ing in the cr2 register: C select the timer clock (cc[1:0]) (see table 17 clock control bits ). C select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull- up without interrupt if this configuration is availa- ble). when an input capture occurs: C icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 46 ). C a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only input capture 2 can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. moreover if one of the icap i pins is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with interrupt genera- tion in order to measure events that go beyond the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr st72321r/ar 73/178 16-bit timer (contd) figure 45. input capture block diagram figure 46. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the rising edge is the a ctive edge. st72321r/ar 74/178 16-bit timer (contd) 10.4.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the oc i e bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. C select the timer clock (cc[1:0]) (see table 17 clock control bits ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). C a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 17 clock control bits ) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * f cpu presc d oc i r = d t * f ext st72321r/ar 75/178 16-bit timer (contd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 48 on page 76 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 49 on page 76 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. figure 47. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 st72321r/ar 76/178 16-bit timer (contd) figure 48. output compare timing diagram, f timer =f cpu /2 figure 49. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) st72321r/ar 77/178 16-bit timer (contd) 10.4.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 17 clock control bits ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the val- ue fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 17 clock control bits ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 50 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level olvl2 is dedi- cated to the one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72321r/ar 78/178 16-bit timer (contd) figure 50. one pulse mode timing example figure 51. pulse width modulation mode timing example with 2 output compare functions note: on timers with only 1 output compare register, a fixed frequency pwm signal can be generated us- ing the output compare and the counter overflow to define the pulse length. counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2 st72321r/ar 79/178 16-bit timer (contd) 10.4.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r regis- ter, and so this functionality can not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values writ- ten in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if (olvl1=0 and olvl2=1) using the formula in the oppo- site column. 3. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with the oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. C set the pwm bit. C select the timer clock (cc[1:0]) (see table 17 clock control bits ). if olvl1=1 and olvl2=0 the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 17 clock control bits ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 51 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72321r/ar 80/178 16-bit timer (contd) 10.4.4 low power modes 10.4.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 10.4.6 summary of timer modes 1) see note 4 in section 10.4.3.5 one pulse mode 2) see note 5 in section 10.4.3.5 one pulse mode 3) see note 4 in section 10.4.3.6 pulse width modulation mode mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with exit from halt mode capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no st72321r/ar 81/178 16-bit timer (contd) 10.4.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 st72321r/ar 82/178 16-bit timer (contd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer re- mains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer re- mains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 17. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11 st72321r/ar 83/178 16-bit timer (contd) control/status register (csr) read only (except bit 2 r/w) reset value: xxxx x0xx (xxh) bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disa- bled the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, must be kept cleared. 70 icf1 ocf1 tof icf2 ocf2 timd 0 0 st72321r/ar 84/178 16-bit timer (contd) input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72321r/ar 85/178 16-bit timer (contd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72321r/ar 86/178 16-bit timer (contd) table 18. 16-bit timer register map and reset values 1 these bits are not used in timer a and must be kept cleared. address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 x ocf1 x tof x icf2 x ocf2 x timd 0 - x - x timer a: 34 timer b: 44 ic1hr reset value msb - ------ lsb - timer a: 35 timer b: 45 ic1lr reset value msb - ------ lsb - timer a: 36 timer b: 46 oc1hr reset value msb - ------ lsb - timer a: 37 timer b: 47 oc1lr reset value msb - ------ lsb - timer a: 3e timer b: 4e oc2hr reset value msb - ------ lsb - timer a: 3f timer b: 4f oc2lr reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ic2hr reset value msb - ------ lsb - timer a: 3d timer b: 4d ic2lr reset value msb - ------ lsb - st72321r/ar 87/178 10.5 serial peripheral interface (spi) 10.5.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves however the spi interface can not be a master in a multi-master system. 10.5.2 main features n full duplex synchronous transfers (on 3 lines) n simplex synchronous transfers (on 2 lines) n master or slave operation n six master mode frequencies (f cpu /4 max.) n f cpu /2 max. slave mode frequency n ss management by software or hardware n programmable clock polarity and phase n end of transfer interrupt flag n write collision, master mode fault and overrun flags 10.5.3 general description figure 52 shows the serial peripheral interface (spi) block diagram. there are 3 registers: C spi control register (spicr) C spi control/status register (spicsr) C spi data register (spidr) the spi is connected to external devices through 3 pins: C miso: master in / slave out data C mosi: master out / slave in data C sck: serial clock out by spi masters and in- put by spi slaves Css : slave select: this input signal acts as a chip select to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master mcu. figure 52. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 st72321r/ar 88/178 serial peripheral interface (contd) 10.5.3.1 functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 53 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this implies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 56 ) but master and slave must be programmed with the same timing mode. figure 53. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software st72321r/ar 89/178 serial peripheral interface (contd) 10.5.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 55 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: Css internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 54 ): if cpha=1 (data latched on 2nd clock edge): Css internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): Css internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 10.5.5.3 ). figure 54. generic ss timing diagram figure 55. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin st72321r/ar 90/178 serial peripheral interface (contd) 10.5.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following two steps in order (if the spicsr register is not written first, the spicr register setting may be not taken into account): 1. write to the spicsr register: C select the clock frequency by configuring the spr[2:0] bits. C select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 56 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. C either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 2. write to the spicr register: C set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 10.5.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 10.5.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: C select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 56 ). note: the slave must have the same cpol and cpha settings as the master. C manage the ss pin as described in section 10.5.3.2 and figure 54 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to e nable the spi i/o functions. 10.5.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 10.5.5.2 ). st72321r/ar 91/178 serial peripheral interface (contd) 10.5.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 56 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 56 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 56. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) st72321r/ar 92/178 serial peripheral interface (contd) 10.5.5 error flags 10.5.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: C the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. C the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. 10.5.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: C the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 10.5.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 10.5.3.2 slave select management . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 57 ). figure 57. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result st72321r/ar 93/178 serial peripheral interface (contd) 10.5.5.4 single master systems a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 58 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. figure 58. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu st72321r/ar 94/178 serial peripheral interface (contd) 10.5.6 low power modes 10.5.6.1 using the spi to wakeup the mcu from halt mode in slave configuration, the spi is able to wakeup the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is run- ning (interrupt vector fetch). if multiple data trans- fers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. so if slave selec- tion is configured as external (see section 10.5.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 10.5.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the mcu is woken up by an interrupt with exit from halt mode ca- pability. the data received is subsequently read from the spidr register when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no st72321r/ar 95/178 serial peripheral interface (contd) 10.5.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1, modf=1 or ovr=1 in the spicsr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.5.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the ex- ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 19 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.5.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 19. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 st72321r/ar 96/178 serial peripheral interface (contd) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision status (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 57 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 10.5.5.2 ). an interrupt is generated if spie = 1 in spicsr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 10.5.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicsr register. this bit is cleared by a software sequence (an ac- cess to the spicsr register while modf=1 fol- lowed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 10.5.3.2 slave select management . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a chip select by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will initiate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 52 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0 st72321r/ar 97/178 serial peripheral interface (contd) table 20. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 or 0 modf 00 sod 0 ssm 0 ssi 0 st72321r/ar 98/178 10.6 serial communications interface (sci) 10.6.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 10.6.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n dual baud rate generator systems n independently programmable transmit and receive baud rates up to 500k baud. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: C address bit (msb) C idle line n muting function for multiprocessor configurations n separate enable bits for transmitter and receiver n four error detection flags: C overrun error C noise error C frame error C parity error n five interrupt sources with flags: C transmit data register empty C transmission complete C receive data register full C idle line received C overrun error detected n parity control: C transmits parity bit C checks parity of received data byte n reduced power consumption mode 10.6.3 general description the interface is externally connected to another device by two pins (see figure 60 ): C tdo: transmit data output. when the transmit- ter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. C rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: C an idle line prior to transmission or reception C a start bit C a data word (8 or 9 bits) least significant bit first C a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: C a conventional type for commonly-used baud rates, C an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. st72321r/ar 99/178 serial communications interface (contd) figure 59. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2 st72321r/ar 100/178 serial communications interface (contd) 10.6.4 functional description the block diagram of the serial control interface, is shown in figure 59 . it contains 6 dedicated reg- isters: C two control registers (scicr1 & scicr2) C a status register (scisr) C a baud rate register (scibrr) C an extended prescaler receiver register (scier- pr) C an extended prescaler transmitter register (sci- etpr) refer to the register descriptions in section 10.6.7 for the definitions of each bit. 10.6.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg- ister (see figure 59 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of 1s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving 0s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra 1 bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 60. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra 1 data frame break frame start bit extra 1 data frame next data frame next data frame st72321r/ar 101/178 serial communications interface (contd) 10.6.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be- tween the internal bus and the transmit shift regis- ter (see figure 59 ). procedure C select the m bit to define the word length. C select the desired baud rate using the scibrr and the scietpr registers. C set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. C access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: C the tdr register is empty. C the data transfer is beginning. C the next data can be written in the scidr regis- ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the scidr register places the data di- rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit l oads the shift register with a break character. the break frame length depends on the m bit (see figure 60 ). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr. st72321r/ar 102/178 serial communications interface (contd) 10.6.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be- tween the internal bus and the received shift regis- ter (see figure 59 ). procedure C select the m bit to define the word length. C select the desired baud rate using the scibrr and the scierpr registers. C set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: C the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. C an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. C the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the spi han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the rdr register as long as the rdrf bit is not cleared. when a overrun error occurs: C the or bit is set. C the rdr content will not be lost. C the shift register will be overwritten. C an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr reg- ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: C the nf is set at the rising edge of the rdrf bit. C data is transferred from the shift register to the scidr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a scisr register read oper- ation followed by a scidr register read operation. framing error a framing error is detected when: C the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. C a break is received. when the framing error is detected: C the fe bit is set by hardware C data is transferred from the shift register to the scidr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper- ation followed by a scidr register read operation. st72321r/ar 103/178 serial communications interface (contd) figure 61. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register st72321r/ar 104/178 serial communications interface (contd) 10.6.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 10.6.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 61 . the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by set- ting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,.. 255 (see scierpr register) 10.6.4.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupts are inhibited. a muted receiver may be awakened by one of the following two ways: C by idle line detection if the wake bit is reset, C by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a 1 as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution : in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu=1) and a address mark wake up event occurs (rwu is reset) before the write operation, the rwu bit will be set again by this write operation. consequently the address byte is lost and the sci is not woken up from mute mode. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu st72321r/ar 105/178 serial communications interface (contd) 10.6.4.7 parity control parity control (generation of parity bit in trasmis- sion and and parity chencking in reception) can be enabled by setting the pce bit in the scicr1 reg- ister. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in table 21 . table 21. frame formats legend: sb = start bit, stb = stop bit, pb = parity bit note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity: the parity bit is calculated to obtain an even number of 1s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of 1s inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in- terface checks if the received data byte has an even number of 1s if even parity is selected (ps=0) or an odd number of 1s if odd parity is se- lected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is gen- erated if pie is set in the scicr1 register. 10.6.5 low power modes 10.6.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc register is reset (rim instruc- tion). m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb | mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmit- ting/receiving until halt mode is exit- ed. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission com- plete tc tcie yes no received data ready to be read rdrf rie yes no overrun error detected or yes no idle line detected idle ilie yes no parity error pe pie yes no st72321r/ar 106/178 serial communications interface (contd) 10.6.7 register description status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register fol- lowed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data will not be transferred to the shift reg- ister unless the tdre bit is cleared. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a pre- amble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift register will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a parity error oc- curs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inter- rupt is generated if pie=1 in the scicr1 register. 0: no parity error 1: parity error 70 tdre tc rdrf idle or nf fe pe st72321r/ar 107/178 serial communications interface (contd) control register 1 (scicr1) read/write reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (gener- ation and detection). when the parity control is en- abled, the computed parity is inserted at the msb position (9th bit if m=1; 8th bit if m=0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmis- sion). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected after the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled. 70 r8 t8 scid m wake pce ps pie st72321r/ar 108/178 serial communications interface (contd) control register 2 (scicr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: C during transmission, a 0 pulse on the te bit (0 followed by 1) sends a preamble (idle line) after the current word. C when te is set there is a 1 bit-time delay before the transmission starts. caution: the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set). bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, otherwise it cannot function in mute mode with wakeup by idle line detection. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to 1 and then to 0, the transmitter will send a br eak word at the end of the current word. 70 tie tcie rie ilie te re rwu sbk st72321r/ar 109/178 serial communications interface (contd) data register (scidr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 59 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 59 ). baud rate register (scibrr) read/write reset value: 00xx xxxx (xxh) bits 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 rr dividing factor scr2 scr1 scr0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 st72321r/ar 110/178 serial communications interface (contd) extended receive prescaler division register (scierpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bits 7:0 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 61 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (scietpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bits 7:0 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 61 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 22. baudrate selection 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 16, pr= 3 tr (or rr)= 2, pr=13 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr)= 1, pr=1 14400 ~14285.71 st72321r/ar 111/178 serial communication interface (contd) table 23. sci register map and reset values address (hex.) register label 76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value scp1 0 scp0 0 sct2 x sct1 x sct0 x scr2 x scr1 x scr0 x 0053h scicr1 reset value r8 x t8 x scid 0 m x wake x pce 0 ps 0 pie 0 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scierpr reset value msb 0000000 lsb 0 0057h scipetpr reset value msb 0000000 lsb 0 st72321r/ar 112/178 10.7 i 2 c bus interface (i2c) 10.7.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, pro- tocol, arbitration and timing. it supports fast i 2 c mode (400khz). 10.7.2 main features n parallel-bus/i 2 c protocol converter n multi-master capability n 7-bit/10-bit addressing n transmitter/receiver flag n end-of-byte transmission flag n transfer problem detection i 2 c master features: n clock generation n i 2 c bus busy flag n arbitration lost flag n end of byte transmission flag n transmitter/receiver flag n start bit detection flag n start and stop generation i 2 c slave features: n stop bit detection n i 2 c bus busy flag n detection of misplaced start or stop condition n programmable i 2 c address detection n transfer problem detection n end-of-byte transmission flag n transmitter/receiver flag 10.7.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by soft- ware. mode selection the interface can operate in the four following modes: C slave transmitter/receiver C master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master ca- pability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recog- nising its own address (7 or 10-bit), and the gen- eral call address. the general call address de- tection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start con- dition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 62 . figure 62. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b st72321r/ar 113/178 i 2 c bus interface (contd) acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call ad- dress can be selected by software. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast i 2 c (100- 400khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 63. i 2 c interface block diagram data register (dr) data shift register comparator own address register 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai own address register 2 (oar2) st72321r/ar 114/178 i 2 c bus interface (contd) 10.7.4 functional description refer to the cr, sr1 and sr2 registers in section 10.7.7 . for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. 10.7.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparision includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: C acknowledge pulse if the ack bit is set. C evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister, holding the scl line low (see figure 64 transfer sequencing ev1). next, in 7-bit mode read the dr register to deter- mine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address se- quence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1) . slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the inter- nal shift register. after each byte the interface gen- erates in sequence: C acknowledge pulse if the ack bit is set C evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 64 transfer se- quencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 64 transfer sequencing ev3). when the acknowledge pulse is received: C the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop con- dition is generated by the master. the interface detects this condition and sets: C evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 reg- ister (see figure 64 transfer sequencing ev4). error cases C berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. C af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. note : in both cases, scl line is not held low; how- ever, sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to release both lines by software. st72321r/ar 115/178 i 2 c bus interface (contd) how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. 10.7.4.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condi- tion. once the start condition is sent: C the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address, holding the scl line low (see figure 64 transfer sequencing ev5). slave address transmission then the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the follow- ing event: C the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register, holding the scl line low (see figure 64 transfer se- quencing ev9). then the second address byte is sent by the inter- face. after completion of this transfer (and acknowledge from the slave if the ack bit is set): C the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fig- ure 64 transfer sequencing ev6). next the master must enter receiver or transmit- ter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr reg- ister via the internal shift register. after each byte the interface generates in sequence: C acknowledge pulse if if the ack bit is set C evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 64 transfer se- quencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. st72321r/ar 116/178 i 2 c bus interface (contd) master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 64 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: C evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gener- ate the stop condition. the interface goes auto- matically back to slave mode (m/sl bit cleared). error cases C berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. C af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. C arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note : in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then neces- sary to release both lines by software. st72321r/ar 117/178 i 2 c bus interface (contd) figure 64. transfer sequencing legend: s=start, s r = repeated start, p=stop, a=acknowledge, na=non-acknowledge, evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev3: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev3-1: evf=1, af=1, btf=1; af is cleared by reading sr1 register. btf is cleared by releasing the lines (stop=1, stop=0) or by writing dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading sr2 register. ev5: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. ev6: evf=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev8: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev9: evf=1, add10=1, cleared by reading sr1 register followed by writing dr register. 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter 10-bit master receiver: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a .... . datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7 st72321r/ar 118/178 i 2 c bus interface (contd) 10.7.5 low power modes 10.7.6 interrupts figure 65. event flags and interrupt generation note : the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc reg- ister is reset (rim instruction). mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite yes no end of byte transfer event btf yes no address matched event (slave mode) adsel yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multimaster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10 st72321r/ar 119/178 i 2 c bus interface (contd) 10.7.7 register description i 2 c control register (cr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes: C when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 C when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. C to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). the 00h general call address is ac- knowledged (01h ignored). 0: general call disabled 1: general call enabled bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). C in master mode: 0: no start generation 1: repeated start generation C in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). C in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. C in slave mode: 0: no stop generation 1: release the scl and sda lines after the cur- rent byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 65 for the relationship between the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 64 ) is de- tected. 70 0 0 pe engc start ack stop ite st72321r/ar 120/178 i 2 c bus interface (contd) i 2 c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described in figure 64 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: C btf=1 (byte received or transmitted) C adsl=1 (address matched in slave mode while ack=1) C sb=1 (start condition generated in master mode) C af=1 (no acknowledge received after byte transmission) C stopf=1 (stop condition detected in slave mode) C arlo=1 (arbitration lost in master mode) C berr=1 (bus error, misplaced start or stop condition detected) C add10=1 (master has sent header byte) C address byte successfully transmitted in mas- ter mode. bit 6 = add10 10-bit addressing in master mode . this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the pe- ripheral is disabled (pe=0). 0: no add10 event occurred. 1: master has sent first address byte (header) bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after de- tection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disa- bled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. this information is still updat- ed when the interface is disabled (pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). C following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 64 ). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. C following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register con- tent or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software read- ing sr1 register or by hardware when the inter- face is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched 70 evf add10 tra busy btf adsl m/sl sb st72321r/ar 121/178 i 2 c bus interface (contd) bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated i 2 c status register 2 (sr2) read only reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardware when the interface los- es the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by soft- ware reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a misplaced start or stop condition. an inter- rupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the in- terface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition bit 0 = gcal general call (slave mode). this bit is set by hardware when a general call ad- dress is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 70 0 0 0 af stopf arlo berr gcal st72321r/ar 122/178 i 2 c bus interface (contd) i 2 c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc[6:0] 7-bit clock divider. these bits select the speed of the bus (f scl ) de- pending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). C standard mode (fm/sm=0): f scl <= 100khz f scl = f cpu /(2x([cc6..cc0]+2)) C fast mode (fm/sm=1): f scl > 100khz f scl = f cpu /(3x([cc6..cc0]+2)) note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register ( dr) read / write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] 8-bit data register. these bits contain the byte to be received or trans- mitted on the bus. C transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. C receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the following data bytes are received one by one after reading the dr register. 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0 st72321r/ar 123/178 i 2 c bus interface (contd) i 2 c own address register (oar1) read / write reset value: 0000 0000 (00h) 7-bit addressing mode bit 7:1 = add[7:1] interface address . these bits define the i 2 c bus address of the inter- face. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is dont care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 10-bit addressing mode bit 7:0 = add[7:0] interface address . these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). i 2 c own address register (oar2) read / write reset value: 0100 0000 (40h) bit 7:6 = fr[1:0] frequency bits. these bits are set by software only when the inter- face is disabled (pe=0). to configure the interface to i 2 c specifed delays select the value corre- sponding to the microcontroller frequency f cpu . bit 5:3 = reserved bit 2:1 = add[9:8] interface address . these are the most significant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. 70 add7 add6 add5 add4 add3 add2 add1 add0 70 fr1 fr0 0 0 0 add9 add8 0 f cpu fr1 fr0 < 6 mhz 0 0 6 to 8 mhz 0 1 st72321r/ar 124/178 i2c bus interface (contd) table 24. i 2 c register map and reset values address (hex.) register label 765 4 3210 0018h i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 0019h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 001ah i2csr2 reset value 0 0 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 001bh i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 001ch i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 001dh i2coar2 reset value fr1 0 fr0 10 0 0 add9 0 add8 00 001eh i2cdr reset value msb 000 0 000 lsb 0 st72321r/ar 125/178 10.8 10-bit a/d converter (adc) 10.8.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 10.8.2 main features n 10-bit conversion n up to 16 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 66 . figure 66. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 div 4 f adc f cpu d1 d0 adcdrl 0 1 00 0000 ch3 div 2 st72321r/ar 126/178 10-bit a/d converter (adc) (contd) 10.8.3 functional description the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v aref (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrh and ad- cdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 10.8.3.1 a/d converter configuration the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: C select the cs[3:0] bits to assign the analog channel to convert. 10.8.3.2 starting the conversion in the adccsr register: C set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: C the eoc bit is set by hardware. C the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrl register 3. read the adcdrh register. this clears eoc automatically. note: the data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion re- sult. to read only 8 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrh register. this clears eoc automatically. 10.8.3.3 changing the conversion channel the application can change channels during con- version. when software modifies the ch[3:0] bits in the adccsr register, the current conversion is stopped, the eoc bit is cleared, and the a/d con- verter starts converting the newly selected chan- nel. 10.8.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions. 10.8.5 interrupts none. mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. st72321r/ar 127/178 10-bit a/d converter (adc) (contd) 10.8.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by hard- ware when software reads the adcdrh register or writes to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. 0: f adc = f cpu /4 1: f adc = f cpu /2 bit 5 = adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion bit 4 = reserved. must be kept cleared. bit 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *the number of channels is device dependent. refer to the device pinout description. data register (adcdrh) read only reset value: 0000 0000 (00h) bit 7:0 = d[9:2] msb of converted analog value data register (adcdrl) read only reset value: 0000 0000 (00h) bit 7:2 = reserved. forced by hardware to 0. bit 1:0 = d[1:0] lsb of converted analog value 70 eoc speed adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d9 d8 d7 d6 d5 d4 d3 d2 70 000000d1d0 st72321r/ar 128/178 10-bit a/d converter (contd) table 25. adc register map and reset values address (hex.) register label 76543210 0070h adccsr reset value eoc 0 speed 0 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 0071h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0072h adcdrl reset value000000 d1 0 d0 0 st72321r/ar 129/178 11 instruction set 11.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 26. st7 addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 st72321r/ar 130/178 instruction set overview (contd) 11.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 11.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 11.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 11.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 11.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st72321r/ar 131/178 instruction set overview (contd) 11.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 27. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 11.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative st72321r/ar 132/178 instruction set overview (contd) 11.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf st72321r/ar 133/178 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > st72321r/ar 134/178 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z st72321r/ar 135/178 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 s ). 12.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v. they are given only as de- sign guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 s ) . 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 67 . figure 67. pin loading conditions 12.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 68 . figure 68. pin input voltage c l st7 pin v in st7 pin st72321r/ar 136/178 12.2 absolute maximum ratings stresses above those listed as absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 voltage characteristics 12.2.2 current characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset , 10k w for i/os). for the same reason, unused i/o pins must not be directly tied to v dd or v ss . 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72321r/ar 138/178 operating conditions (contd) 12.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd , f cpu , and t a . notes: 1. data based on characterization results, not tested in production. 2. when vt por is faster than 100 m s/v, the reset signal is released after a delay of max. 42s after v dd crosses the v it+(lvd) threshold. figure 70. lvd startup behaviour note: when the lvd is enabled, the mcu reaches its authorized operating voltage from a reset state. however, in some devices, the reset state is released when v dd is approximately between 0.8v and 1.5v. as a consequence, the i/os may toggle when v dd is within this window. this may be an issue especially for applications where the mcu drives power components. because flash write access is impossible within this window, the flash memory contents will not be cor- rupted. symbol parameter conditions min typ max unit v it+(lvd) reset release threshold (v dd rise) vd level = high in option byte 4.0 1) 4.2 4.5 v vd level = med. in option byte vd level = low in option byte not applicable v it-(lvd) reset generation threshold (v dd fall) vd level = high in option byte 3.8 4.0 4.25 1) vd level = med. in option byte vd level = low in option byte not applicable v hys(lvd) lvd voltage threshold hysteresis 1) v it+(lvd) -v it-(lvd) 150 200 250 mv vt por v dd rise time 1)2) 6 m s/v t g(vdd) filtered glitch delay on v dd 1) not detected by the lvd 40 ns 5v 1.5v v it+ 0.8v lvd reset v d d window t st72321r/ar 139/178 12.3.3 auxiliary voltage detector (avd) thresholds subject to general operating condition for v dd , f cpu , and t a . 1. data based on characterization results, not tested in production. 12.3.4 external voltage detector (evd) thresholds subject to general operating condition for v dd , f cpu , and t a . 1. data based on characterization results, not tested in production. symbol parameter conditions min typ max unit v it+(avd) 1 t 0 avdf flag toggle threshold (v dd rise) vd level = high in option byte 4.4 1) 4.6 4.9 v vd level = med. in option byte vd level = low in option byte not applicable v it-(avd) 0 t 1 avdf flag toggle threshold (v dd fall) vd level = high in option byte 4.2 4.4 4.65 1) vd level = med. in option byte vd level = low in option byte not applicable v hys(avd) avd voltage threshold hysteresis v it+(avd) -v it-(avd) 200 mv d v it- voltage drop between avd flag set and lvd reset activated v it-(avd) -v it-(lvd) 450 mv symbol parameter conditions min typ max unit v it+(evd) 1 t 0 avdf flag toggle threshold (v dd rise) 1) 1.15 1.26 1.35 v v it-(evd) 0 t 1 avdf flag toggle threshold (v dd fall) 1) 1.1 1.2 1.3 v hys(evd) evd voltage threshold hysteresis v it+(evd) -v it-(evd) 200 mv st72321r/ar 140/178 12.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consump- tion, the two current values must be added (except for halt mode for which the clock is stopped). 12.4.1 run and slow modes (flash devices) figure 71. typical i dd in run vs. f cpu figure 72. typical i dd in slow vs. f cpu notes: 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - progam executed from ram, cpu running with ram access. the increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - css and lvd disabled. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source ( section 12.5.3 and section 12.5.4 ) and the peripheral power consumption ( section 12.4.7 ). symbol parameter conditions typ max 1) unit i dd supply current in run mode 2) (see figure 71 ) 3.8v v dd 5.5v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 ma supply current in slow mode 2) (see figure 72 ) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 0.6 0.7 0.8 1.1 2.7 3.0 3.6 4.0 ma 0 1 2 3 4 5 6 7 8 9 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 8mhz 4mhz 2mhz 1mhz 0.00 0.20 0.40 0.60 0.80 1.00 1.20 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 500khz 250khz 125khz 62.5khz st72321r/ar 141/178 supply current characteristics (contd) 12.4.2 wait and slow wait modes (flash devices) figure 73. typical i dd in wait vs. f cpu figure 74. typical i dd in slow-wait vs. f cpu notes: 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - progam executed from ram, cpu running with ram access. the increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - css and lvd disabled. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source ( section 12.5.3 and section 12.5.4 ) and the peripheral power consumption ( section 12.4.7 ). symbol parameter conditions typ max 1) unit i dd supply current in wait mode 2) (see figure 73 ) 3.8v v dd 5.5v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.0 1.5 2.5 4.5 3.0 4.0 5.0 7.0 ma supply current in slow wait mode 2) (see figure 74 ) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 0.58 0.65 0.77 1.05 1.2 1.3 1.8 2.0 ma 0 1 2 3 4 5 6 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 8mhz 4mhz 2mhz 1mhz 0.00 0.20 0.40 0.60 0.80 1.00 1.20 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) () 500khz 250khz 125khz 62.5khz st72321r/ar 142/178 supply current characteristics (contd) 12.4.3 run and slow modes (rom devices) 12.4.4 wait and slow wait modes (rom devices) notes: 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - progam executed from ram, cpu running with ram access. there is no increase in consumption for if programs are executed in rom - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - css and lvd disabled. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source ( section 12.5.3 and section 12.5.4 ) and the peripheral power consumption ( section 12.4.7 ). symbol parameter conditions typ max 1) unit i dd supply current in run mode 2) 3.8v v dd 5.5v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 ma supply current in slow mode 2) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 0.6 0.7 0.8 1.1 2.7 3.0 3.6 4.0 symbol parameter conditions typ max 1) unit i dd supply current in wait mode 2) 3.8v v dd 5.5v f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.0 1.5 2.5 4.5 3.0 4.0 5.0 7.0 ma supply current in slow wait mode 2) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 0.07 0.1 0.2 0.35 1.2 1.3 1.8 2.0 st72321r/ar 143/178 supply current characteristics (contd) 12.4.5 halt and active-halt modes notes: 1. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load), css and lvd disabled. data based on characterization results, tested in production at v dd max. and f cpu max. 2. data based on characterisation results, not tested in production. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load); clock input (osc1) driven by external square wave, lvd disabled. to obtain the total current consumption of the device, add the clock source consumption ( section 12.5.3 and section 12.5.4 ). 12.4.6 supply and clock managers the previous current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consump- tion, the two current values must be added (except for halt mode). notes: 1. data based on characterisation results, not tested in production. 2. data based on characterization results done with the external components specified in section 12.5.3 and section 12.5.4 , not tested in production. 3. as the oscillator is based on a current source, the consumption does not depend on the voltage. symbol parameter conditions typ max unit i dd supply current in halt mode 1) v dd =5.5v -40c t a +85c 10 m a -40c t a +125c 50 i dd supply current in active-halt mode 2) f osc = 16 mhz, v dd = 5v 650 no max. guaran- teed m a symbol parameter conditions typ max 1) unit i dd(rcint) supply current of internal rc oscillator 625 m a i dd(rcext) supply current of external rc oscillator 2) see section 12.5.4 on page 148 i dd(res) supply current of resonator oscillator 2) & 3) see section 12.5.3 on page 146 i dd(pll) pll supply current v dd = 5v 360 i dd(css) clock security system supply current v dd = 5v 250 i dd(lvd) lvd supply current halt mode, v dd = 5v 150 300 st72321r/ar 144/178 supply current characteristics (contd) 12.4.7 on-chip peripherals measured on s72f521r9t3 on tqfp64 generic board t a = 25c f cpu =4mhz. notes: 1. data based on a differential i dd measurement between reset configuration (timer counter running at f cpu /4) and timer counter stopped (only timd bit set). data valid for one timer. 2. data based on a differential i dd measurement between reset configuration (timer stopped) and timer counter enabled (only tce bit set). 3. data based on a differential i dd measurement between reset configuration (spi disabled) and a permanent spi master communicationat maximum speed (data sent equal to 55h).this measurement includes the pad toggling consumption. 4. data based on a differential i dd measurement between reset configuration (i2c disabled) and a permanent i2c master communication at 100khz (data sent equal to 55h). this measurement include the pad toggling consumption (27kohm external pull-up on clock and data lines). 6. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 1) v dd = 5.0v 50 m a i dd(art) art pwm supply current 2) v dd = 5.0v 75 i dd(spi) spi supply current 3) v dd = 5.0v 400 m a i dd(i2c) i2c supply current 4) v dd = 5.0v 175 i dd(adc) adc supply current when converting 6) v dd = 5.0v 400 m a st72321r/ar 145/178 12.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 12.5.1 general timings 12.5.2 external clock source figure 75. typical application with an external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 3. data based on design simulation and/or technology characteristics, not tested in production. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2 3 12 t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) + 10 10 22 t cpu f cpu =8mhz 1.25 2.75 m s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 75 v dd -1 v dd v v osc1l osc1 input pin low level voltage v ss v ss +1 t w(osc1h) t w(osc1l) osc1 high or low time 3) 5 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l oscx input leakage current v ss v in v dd 1 m a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% st72321r/ar 146/178 clock and timing characteristics (contd) 12.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the reso- nator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). figure 76. typical application with a crystal or ceramic resonator notes: 1. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to crystal/ceramic resonator manufacturer for more details. symbol parameter conditions min max unit f osc oscillator frequency 1) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor 20 40 k w c l1 c l2 recommended load capacitance ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) r s =200 w lp oscillator r s =200 w mp oscillator r s =200 w ms oscillator r s =100 w hs oscillator 22 22 18 15 56 46 33 33 pf symbol parameter conditions typ max unit i 2 osc2 driving current v dd =5v lp oscillator v in =v ss mp oscillator ms oscillator hs oscillator 80 160 310 610 150 250 460 910 m a osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors st72321r/ar 147/178 clock and timing characteristics (contd) notes: 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 m s). 3. contact the supplier for updated product information. oscil. typical crystal or ceramic resonators c l1 [pf] c l2 [pf] t su(osc) [ms] 2) reference 3) freq. characteristic 1) ceramic lp murata csa2.00mg 2mhz d f osc =[0.5% tolerance ,0.3% d ta , 0.3% aging , x.x% correl ]22 22 4 mp csa4.00mg 4mhz d f osc =[0.5% tolerance ,0.3% d ta , 0.3% aging , x.x% correl ]22 22 2 ms csa8.00mtz 8mhz d f osc =[0.5% tolerance ,0.5% d ta , 0.3% aging , x.x% correl ]33 33 1 hs csa16.00mxz040 16mhz d f osc =[0.5% tolerance ,0.3% d ta , 0.3% aging , x.x% correl ] 33 33 0.7 st72321r/ar 148/178 clock characteristics (contd) 12.5.4 rc oscillators the st7 internal clock can be supplied with an rc oscillator. this oscillator can be used with internal or external components (selectable by option byte). figure 77. typical application with rc oscillator notes: 1. data based on design simulation. 2. r ex must have a positive temperature coefficient (ppm/c), carbon resistors should therefore not be used. 3. i cex is the current needed to load the c ex capacitor while osc1 is forced to v ss or 1.5v (rc oscillation voltage range). figure 78. typical f osc(rcint) vs v dd figure 79. typical f osc(rcint) vs t a symbol parameter conditions min typ max unit f osc (rcint) internal rc oscillator frequency see figure 78 and figure 79 t a =25c, v dd =5v 2 3.5 5.6 mhz f osc(rcext) external rc oscillator frequency 1) 5 / (r ex .c ex ) r ex oscillator external resistor 2) 56 100 k w c ex oscillator external capacitor 22 470 pf |i cex | capacitor load current 3) osc1 = v ss or 1.5v 290 350 m a osc2 osc1 f osc c ex r ex external rc internal rc v ref + - v dd current copy voltage generator c ex discharge st72xxx r in c in i cex 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.35 5 5.5 v dd (v) f osc(rcint) (mhz) ta =-45c ta =25c ta =130c 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 -45 0 25 70 130 t a (c) f osc(rcint) (mhz) vdd = 2.4v vdd = 5v st72321r/ar 149/178 clock characteristics (contd) 12.5.5 clock security system (css) note: 1. data based on characterization results. 12.5.6 pll characteristics operating conditions: v dd 3.8 to 5.5v @ t a 0 to 70c 1) or v dd 4.5 to 5.5v @ t a -40 to 125c note: 1. data characterized but not tested. figure 80. pll jitter vs. signal frequency 1 the user must take the pll jitter into account in the application (for example in serial communica- tion or sampling of high frequency signals). the pll jitter is a periodic effect, which is integrated over several cpu cycles. therefore the longer the period of the application signal, the less it will be impacted by the pll jitter. figure 80 shows the pll jitter integrated on appli- cation signals in the range 125khz to 2mhz. at fre- quencies of less than 125khz, the jitter is negligi- ble. note 1: measurement conditions: f cpu = 4mhz, t a = 25c symbol parameter conditions min typ max unit f sfosc safe oscillator frequency 1) 3mhz symbol parameter conditions min typ max unit v dd(pll) pll operating range t a 0 to 70 c 3.8 5.5 v t a -40 to +125 c 4.5 5.5 f osc pll input frequency range 2 4 mhz f cpu / d f cpu instantaneous pll jitter 1) f osc = 4 mhz. 1.0 2.5 % f osc = 2 mhz. 2.5 4.0 % 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2000 1000 500 250 125 application signal frequency (khz) +/-jitter (%) pll on pll off st72321r/ar 150/178 12.6 memory characteristics 12.6.1 ram and hardware registers 12.6.2 flash memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). not tested in production. 2. data based on characterization results, not tested in production. 3. v pp must be applied only during the programming or erasing operation and not permanently for reliability reasons. 4. data based on simulation results, not tested in production. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v dual voltage hdflash memory symbol parameter conditions min 2) typ max 2) unit f cpu operating frequency read mode 0 8 mhz write / erase mode 1 8 v pp programming voltage 3) 4.5v v dd 5.5v 11.4 12.6 v i dd supply current 4) run mode (f cpu = 4mhz) 3 ma write / erase 0 power down mode / halt 1 10 a i pp v pp current 4) read (v pp =12v) 200 write / erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention t a =55c 20 years n rw write erase cycles t a =25c 100 cycles t prog t erase programming or erasing tempera- ture range -40 25 85 c st72321r/ar 151/178 12.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 12.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). n esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. n ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. 12.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/3 which specifies the board and the loading of each pin. notes: 1. data based on characterization results, not tested in production. symbol parameter conditions neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 -1 1.5 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 -1.5 1.5 symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 8/4mhz 16/8mhz s emi peak level v dd = 5v, t a = +25c, tqfp64 14x14 package conforming to sae j 1752/3 0.1mhz to 30mhz 13 13 db m v 30mhz to 130mhz 19 24 130mhz to 1ghz 7 13 sae emi level 2.0 2.5 - st72321r/ar 152/178 emc characteristics (contd) 12.7.3 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 12.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). two models are usually simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. see figure 81 and the following test sequences. human body model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to r. C a discharge from c l through r (body resistance) to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. machine model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to st7. C a discharge from c l to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. C r (machine resistance), in series with s2, en- sures a slow discharge of the st7. absolute maximum ratings figure 81. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c 200 st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator st7 s2 high voltage c l = 200pf pulse generator r=10k~10m w s1 human body model machine model st72321r/ar 153/178 emc characteristics (contd) 12.7.3.2 static and dynamic latch-up n lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 82 . for more details, refer to the an1181 st7 application note. 12.7.3.3 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: C corrupted program counter C unexpected reset C critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). electrical sensitivities figure 82. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c t a = +125c a a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a r ch =50m w r d =330 w c s = 150pf esd hv relay discharge tip discharge return connection generator 2) st7 v dd v ss st72321r/ar 154/178 emc characteristics (contd) 12.7.4 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 83 and figure 84 for standard pins and in figure 85 and figure 86 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: C a diode to v dd (3a) and a diode from v ss (3b) C a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: C a resistor in series with the pad (1) C a diode to v dd (2a) and a diode from v ss (2b) C a protection device between v dd and v ss (4) figure 83. positive stress on a standard pad vs. v ss figure 84. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path st72321r/ar 155/178 emc characteristics (contd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completely absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss , v ssa , ...) and power supply (v dd , v aref , ...) are available for any reason (better noise immunity...), the structure shown in figure 87 is implemented to protect the device against esd. figure 85. positive stress on a true open drain pad vs. v ss figure 86. negative stress on a true open drain pad vs. v dd figure 87. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v aref v ssa v aref v dd v ss back to back diode between grounds v ssa st72321r/ar 156/178 12.8 i/o port pin characteristics 12.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 88. connecting unused i/o pins figure 89. typical i pu vs. v dd with v in =v ss notes: 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 3. when the current limitation is not possible, the v in maximum must be respected, otherwise refer to i inj(pin) specifica- tion. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72321r/ar 158/178 i/o port pin characteristics (contd) figure 93. typical v ol vs. v dd (standard) figure 94. typical v ol vs. v dd (high-sink) figure 95. typical v dd -v oh vs. v dd 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=5ma ta= -4 5c ta= 25c ta= 95c ta= 140c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 22.533.544.555.56 vdd(v) vol(v) at iio=2ma ta=-45c ta=25c ta=95c ta=140c 0 0.1 0.2 0.3 0.4 0.5 0.6 22.53 3.544.555.56 vdd(v ) vol(v) at iio=8ma ta= 140c ta=95c ta=25c ta=-45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 22.533.54 4.555.56 vdd(v) vol(v) at iio=20ma ta= 140 c ta=95 c ta=25 c ta=-45c 0 1 2 3 4 5 6 22.533.544.555.56 vdd(v) vdd-voh(v) at iio=-5m a ta= -45c ta= 25c ta= 95c ta= 140c 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vdd-voh(v) at iio=-2ma ta= -45c ta= 25c ta= 95c ta= 140c st72321r/ar 159/178 12.9 control pin characteristics 12.9.1 asynchronous reset pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 96. typical application with reset pin 6)7)8) notes: 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. 3. the i io current sunk must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on the reset pin with a duration below t h(rstl)in can be ignored. 5. the reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en- vironments. 6. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). 7. whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.9.1 . otherwise the reset will not be taken into account internally. 8. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up for example) is less than the absolute maximum value specified for i inj(reset) in section 12.2.2 on page 136 . 9. data guaranteed by design, not tested in production. symbol parameter conditions min typ max unit v il input low level voltage 1) 0.16xv dd v v ih input high level voltage 1) 0.85xv dd v hys schmitt trigger voltage hysteresis 2) 2.5 v ol output low level voltage 3) v dd =5v i io =+5ma 0.5 1.2 i io =+2ma 0.2 0.5 i io input current on reset pin 2 tbd ma r on weak pull-up equivalent resistor 20 30 120 k w t w(rstl)out generated reset pulse duration external pin 0 42 9) m s internal reset sources 20 30 42 9) m s t h(rstl)in external reset pulse hold time 4) 2.5 m s t g(rstl)in filtered glitch duration 5) 200 ns 0.01 m f v dd 0.01 m f external reset circuit 5) user v dd 4.7k w required if lvd is disabled recommended if lvd is disabled st72xxx pulse generator filter r on v dd watchdog lvd reset internal reset st72321r/ar 160/178 control pin characteristics (contd) 12.9.2 iccsel/v pp pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 97. two typical applications with iccsel/v pp pin 2) notes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. when icc mode is not required by the application iccsel/v pp pin must be tied to v ss . 12.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (out- put compare, input capture, external clock, pwm output...). 12.10.1 8-bit pwm-art auto-reload timer 12.10.2 16-bit timer symbol parameter conditions min max unit v il input low level voltage 1) flash versions v ss 0.2 v rom versions v ss 0.3xv dd v ih input high level voltage 1) flash versions v dd -0.1 12.6 rom versions 0.7xv dd v dd i l input leakage current v in =v ss 1 m a symbol parameter conditions min typ max unit t res(pwm) pwm resolution time 1t cpu f cpu =8mhz 125 ns f ext art external clock frequency 0 f cpu /2 mhz f pwm pwm repetition rate 0 f cpu /2 res pwm pwm resolution 8 bit v os pwm/dac output step voltage v dd =5v, res=8-bits 20 mv iccsel/v pp st72xxx 10k w programming tool v pp st72xxx symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit st72321r/ar 161/178 12.11 communication interface characteristics 12.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 98. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 90 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in st72321r/ar 162/178 communication interface characteristics (contd) figure 99. spi slave timing diagram with cpha=1 1) figure 100. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=1 mosi input miso output cpha=1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) st72321r/ar 163/178 communication interface characteristics (contd) 12.11.2 i 2 c - inter ic control interface subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table. figure 101. typical application with i 2 c bus and timing diagram 4) notes: 1. data based on standard i 2 c protocol requirement, not tested in production. 2. the device must internally provide a hold time of at least 300ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 4. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter standard mode i 2 c fast mode i 2 c unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 m s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 m s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 ns t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 ms c b capacitive load for each bus line 400 400 pf repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda sck 4.7k w sdai st72xxx scli v dd 100 w 100 w v dd 4.7k w i 2 cbus st72321r/ar 164/178 12.12 10-bit adc characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 102. r ain max. vs f adc with c ain =0pf 4) figure 103. recommended c ain & r ain values. 5) figure 104. typical a/d converter application notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k w ). data based on characterization results, not tested in production. 4. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad ca- pacitance (3pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 5. this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization and to allow the use of a larger serial resistor (r ain) . symbol parameter conditions min typ 1) max unit f adc adc clock frequency 0.4 2 mhz v aref analog reference voltage 2) 0.7*v dd 5.5 v v ain conversion voltage range 3) v ssa v aref i l input leakage current for analog input -40c t a 85c range 250 na other t a ranges 1 m a r ain external input impedance see figure 102 and figure 103 3)4)5) k w c ain external capacitor on analog input pf f ain variation freq. of analog input signal hz c adc internal sample and hold capacitor 12 pf t stab stabilization time after adc enable f cpu =8mhz, speed=0 f adc =2mhz 0 5) m s t adc conversion time (sample+hold) 7.5 - no of sample capacitor loading cycles - no. of hold conversion cycles 4 11 1/f adc 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 2 mhz 1 mhz 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i l 1 m a v t 0.6v v t 0.6v c adc 6pf v ain r ain 10-bit a/d conversion 2k w( max ) c ain st72321r/ar 165/178 adc characteristics (contd) 12.12.0.1 analog power supply and reference pins depending on the mcu pin count, the package may feature separate v aref and v ssa analog power supply pins. these pins supply power to the a/d converter cell and function as the high and low reference voltages for the conversion. in smaller packages v aref and v ssa pins are not available and the analog supply and reference pads are in- ternally bonded to the v dd and v ss pins. separation of the digital and analog power pins al- low board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see section 12.12.0.2 general pcb design guidelines ). 12.12.0.2 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. C use separate digital and analog planes. the an- alog ground plane should be connected to the digital ground plane via a single point on the pcb. C filter power to the analog power planes. it is rec- ommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and optionally, if needed 10pf capacitors as close as possible to the st7 power supply pins and a 1 to 10f ca- pacitor close to the power source (see figure 105 ). C the analog and digital power supplies should be connected in a star nework. do not use a resis- tor, as v aref is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. C properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital out- puts on the same i/o port as the a/d input being converted. figure 105. power supply filtering v ss v dd 0.1 m f 10pf v dd st72xxx v aref v ssa power supply source st7 digital noise filtering external noise filtering 1 to 10 m f 0.1 m f 10pf (if needed) (if needed) st72321r/ar 166/178 10-bit adc characteristics (contd) 12.12.1 adc accuracy conditions: v dd =5v notes: 1. injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. analog pins can be protected against negative injection by adding a schottky diode (pin to ground). injecting negative current on digital input pins degrades adc accuracy especially if performed on a pin close to the analog input pins. any positive injection current within the limits specified for i inj(pin) and s i inj(pin) in section 12.8 does not affect the adc accuracy. 2. data based on characterization results, monitored in production. figure 106. adc accuracy characteristics symbol parameter conditions typ max unit |e t | total unadjusted error 1) 4 lsb e o offset error 1) 3 3.5 2) e g gain error 1) -0.5 -2 2) |e d | differential linearity error 1) cpu in run mode @ f adc 2 mhz. 1.5 4.5 2) |e l | integral linearity error 1) cpu in run mode @ f adc 2 mhz. 1.5 4.5 2) e o e g 1lsb ideal 1lsb ideal v aref v ssa C 1024 -------------------------------------------- = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v aref v ssa st72321r/ar 167/178 13 package characteristics 13.1 package mechanical data figure 107. 64-pin thin quad flat package figure 108. 64-pin thin quad flat package dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.80 0.031 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 c h l l1 e b a a1 a2 e e1 d d1 dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.50 0.020 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 a a2 a1 c h l1 l e e1 d d1 e b st72321r/ar 168/178 13.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) tqfp64 14x14 tqfp64 10x10 47 50 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st72321r/ar 169/178 13.3 soldering and glueability information recommended soldering information given only as design guidelines. figure 109. recommended wave soldering profile (with 37% sn and 63% pb) figure 110. recommended reflow soldering oven profile (mid jedec) recommended glue for smd plastic packages dedicated to molding compound with silicone: n heraeus: pd945, pd955 n loctite: 3615, 3298 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=235+/-5c for 25 sec st72321r/ar 170/178 14 st72321r/ar device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom). flash devices are shipped to customers with a default content, while rom factory coded parts contain the code sup- plied by the customer. this implies that flash de- vices have to be configured by the customer using the option bytes while the rom devices are facto- ry-configured. 14.1 flash option bytes the option bytes allow the hardware configuration of the microcontroller to be selected. they have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 programming tool). the default con- tent of the flash is fixed to ffh. to program the flash devices directly using icp, flash devices are shipped to customers with the internal rc clock source enabled. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). option byte 0 opt7= wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt6= wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt5 = css clock security system on/off this option bit enables or disables the clock secu- rity system function (css) which includes the clock filter and the backup safe oscillator. 0: css enabled 1: css disabled opt4:3= vd[1:0] voltage detection these option bits enable the voltage detection block (lvd, and avd) with a selected threshold for the lvd and avd (evd+avd). opt1= pkg0 package selection bit 0 this option bit is used to select the package (see table in pkg1 option bit description). static option byte 0 70 static option byte 1 70 wdg css vd pkg0 fmp_r pkg1 rstc osctype oscrange plloff halt sw 10 10 2 10 default 1 11001111 1 10 1 1 1 1 selected low voltage detector vd1 vd0 lvd and avd off 1 1 not used (lowest threshold: (v dd ~3v) 1 0 not used (med. threshold v dd ~3.5v) 0 1 highest voltage threshold (v dd ~4v) 0 0 st72321r/ar 171/178 st72321r/ar device configuration and ordering information (contd) opt0= fmp_r flash memory read-out protection this option indicates if the user flash memory is protected against read-out piracy. this protection is based on read and a write protection of the memory in test modes and icp mode. erasing the option bytes when the fmp_r option is selected induce the whole user memory erasing first. 0: read-out protection enabled 1: read-out protection disabled option byte 1 opt7= pkg1 package selection bit 1 this option bit, with the pkg0 bit, selects the pack- age. note: on the chip, each i/o port has 8 pads. pads that are not bonded to external pins are in input pull-up configuration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. opt6 = rstc reset clock cycle selection this option bit selects the number of cpu cycles applied during the r eset phase and w hen exiting halt mode. for resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles note: when the css is enabled, the device starts to count immediately using the backup oscillator. opt5:4 = osctype[1:0] oscillator type these option bits select the st7 main clock source type. opt3:1 = oscrange[2:0] oscillator range when the resonator oscillator type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. otherwise, these bits are used to select the normal operating frequency range. opt0 = pll off pll activation this option bit activates the pll which allows mul- tiplication by two of the main input clock frequency. the pll must not be used with the internal rc os- cillator. the pll is guaranteed only with an input frequency between 2 and 4mhz. 0: pll x2 enabled 1: pll x2 disabled caution : the pll can be enabled only if the osc range (opt3:1) bits are configured to mp - 2~4mhz. otherwise, the device functionali- ty is not guaranteed. version selected package pkg 1 pkg 0 (a)r tqfp64 1 0 clock source osctype 10 resonator oscillator 0 0 external rc oscillator 0 1 internal rc oscillator 1 0 external source 1 1 typ. freq. range oscrange 210 lp 1~2mhz 0 0 0 mp 2~4mhz 0 0 1 ms 4~8mhz 0 1 0 hs 8~16mhz 0 1 1 st72321r/ar 172/178 st72321r/ar device configuration and ordering information (contd) 14.2 device ordering information and transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 111. rom factory coded device types table 28. orderable flash device types device package temp. range xxx / code name (defined by stmicroelectronics) 1= 0 to +70 c 5= -10 to +85 c 6= -40 to +85 c c = -40 to +125 c t= plastic thin quad flat pack st72321r9, ST72321R7, st72321r6 st72321ar9, st72321ar7, st72321ar6 part number program memory (bytes) temp. range package st72f321r9tc 60kb flash - 40c +125c tqfp64 14 x 14 st72f321r9t6 -40c +85c tqfp64 14 x 14 st72f321ar9tc -40c +125c tqfp64 10 x 10 st72f321ar9t6 -40c +85c tqfp64 10 x 10 st72f321r7t6 48kb flash -40c +85c tqfp64 14 x 14 st72f321ar7t6 tqfp64 10 x 10 st72f321r6t6 32kb flash tqfp64 14 x 14 st72f321ar6t6 tqfp64 10 x 10 st72321r/ar 173/178 st72321r/ar device configuration and ordering information (contd) st72321r/ar microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): conditioning (check only one option): temp. range (do not check for die product: special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max) authorized characters are letters, digits, '.', '-', '/' and spaces only. clock source selection: [ ] resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] rc network: 1 [ ] internal [ ] external [ ] external clock pll 1 [ ] disabled [ ] enabled clock security system: [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] enabled: [ ] highest threshold reset delay [ ] 256 cycles [ ] 4096 cycles watchdog selection: [ ] software activation [ ] hardware activation halt when watchdog on: [ ] reset [ ] no reset readout protection: [ ] disabled [ ] enabled date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pll must not be enabled if internal rc network is selected --------------------------------- rom device: --------------------------------- | | ------------------------------------- 60k ------------------------------------- || ------------------------------------- 48k ------------------------------------- || --------------------------------- - 32k --------------------------------- - tqfp64 14x14: | [ ] st72321r9 | [ ] ST72321R7 | [ ] st72321r6 tqfp64 10x10: | [ ] st72321ar9 | [ ] st72321ar7 | [ ] st72321ar6 --------------------------------- die form: --------------------------------- | | --------------------------------------- 60k --------------------------------------- || -------------------------------------- 48k -------------------------------------- || ---------------------------------- 32k ---------------------------------- - 64-pin: | [ ] | [ ] | [ ] ------------------------------------------------------------------------ packaged product ------------------------------------------------------------------------ | | ----------------------------------------------------- die product (dice tested at 25c only) ----------------------------------------------------- [ ] tape & reel [ ] tray | [ ] tape & reel | [ ] inked wafer | [ ] sawn wafer on sticky foil [ ] 0c to +70c [ ] -10c to +85c [ ] -40c to +105c [ ] -40c to +85c [ ] -40c to +125c st72321r/ar 174/178 device configuration and ordering information (contd) 14.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. tools from these manufacturers include c compli- ers, emulators and gang programmers. st emulators the emulator is delivered with everything (probes, teb, adapters etc.) needed to start emulating the devices. to configure the emulator to emulate dif- ferent st7 subfamily devices, the active probe for the st7 emu3 can be changed and the st7emu3 probe is designed for easy interchange of tebs (target emulation board). see table 29 for more details. 14.3.1 socket and emulator adapter information for information on the type of socket that is sup- plied with the emulator, refer to the suggested list of sockets in table 30 . note: before designing the board layout, it is rec- ommended to check the overall dimensions of the socket as they may be greater than the dimen- sions of the device. for footprint and other mechanical information about these sockets and adapters, refer to the manufacturers datasheet (www.yamaichi.de for tqfp64 10 x 10 and www.cabgmbh.com for tqfp64 14 x 14).. table 29. stmicroelectronics development tools note : 1. flash programming interface for flash devices. table 30. suggested list of socket types supported products st7 evaluation board st7 emulator active probe & t.e.b. st7 programming board st72321(a)r, st72f321(a)r st7mdt2-train/ eu st7mdt2- train/us st7mdt2-train/ uk st7mdt20m- emu3 st7mdt20m- teb st7mdt20m-epb/eu st7mdt20m-epb/us st7mdt20m-epb/uk device socket (supplied with st7mdt20m- emu3) emulator adapter (supplied with st7mdt20m-emu3) tqfp64 14 x14 cab 3303262 cab 3303351 tqfp64 10 x10 yamaichi ic149-064-*75-*5 yamaichi icp-064-6 st72321r/ar 175/178 14.4 st7 application notes identification description example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communicating between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripheral registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 permanent magnet dc motor drive. an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 using the st7 spi to emulate a 16-bit slave an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 application to st72f264 product optimization st72321r/ar 176/178 an 982 using st7 with ceramic renator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1477 emulated data eeprom with xflash memory an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscil- lator programming and tools an 978 key features of the stvd7 st7 visual debug package an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus identification description st72321r/ar 177/178 15 summary of changes revision main changes date 1.6 removed 80-pin device package changed itspr register names to ispr in table 2 on page 13 modified css functional description (glitch filtering with pll on) in section 6.4.3 on page 29 removed avd interrupt exit from halt capability in section 6.4.4.1 on page 29 v pp absolute max changed from 14 to 13v in section 12.2 on page 136 . modified i dd max values in section 12.4 on page 140 removed description of low and medium thresholds. updated lvd min rise time rate. added note and figure on lvd startup behaviour in section 12.3 on page 137 updated adc accuracy data and modified note on negative current injection in section 10.8 on page 125 updated pll characteristics section 12.5.6 on page 149 external reset stretch min value changed to 0. in section 12.9 on page 159 changed presentation of option bytes: byte 0 is displayed left of byte 1. option byte default value changed (avd/lvd on) in section section 14.1 on page 170 oct 02 st72321r/ar 178/178 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com |
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